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Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 1 Status of OTIS Outer Tracker Time Information.

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Presentation on theme: "Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 1 Status of OTIS Outer Tracker Time Information."— Presentation transcript:

1 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 1 Status of OTIS Outer Tracker Time Information System LHCb Week Rio 2001, Sept.17 – Sept. 21 OTIS GROUP, Heidelberg University

2 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 2 LHCb at Cern CernLHCb

3 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 3 OTIS TDC Outer Tracker Time Information System Ó3.250 OTIS-TDCs with 32 channels each Ó4 OTIS TDCs are connected to one GOL fast serializer one fibre per 128 channels ÓRadiation hard layout 0.25 µm ÓDLL fine time resolution 6 bit ÓDual Ported Memory with 1.2 Gb/s, 240 bit width low power design ÓSynchronous clock driven readout

4 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 4 LHCb OTIS TDC

5 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 5 Delay Locked Loop Test chip for MEMORY and DLL with MUX: OTISMEM1.0, submitted February 2001 Chip OTISMEM1.0 received and tested: Preliminary results available Ó2nd DLL prototype, contains: ÓDelay chain with 32 stages 2 taps each ÓMean delay per tap 25ns/64 = 390 ps ÓCurrently Hit Register for only one channel with 64 bit multiplexed to 4 pads

6 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 6 DLL Lock Time ÓLock Time is below 1µs DLL Out Clock In Phase Difference Control Voltage DLL

7 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 7 DLL Lock Range ÓLock Range = 29…56MHz at 300K Ósimulated Lock Range 30…50MHz (Within an 10% error) ÓSpec is 30…50MHz at 300K OK !!! ÓDynamic Range of Control Voltage 1V Vctrl/mV Dynamic Range

8 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 8 DLL Temperature Range ÓMeasurement of Temperature Range ÓControl Voltage inside Dynamic Range for all tested Temperatures at 40 MHz Vctrl/mV Dynamic Range

9 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 9 DLL Differential Non Linearity ÓDifferential Non-Linearity (DNL) preliminary: Ó0.79bins (~310ps) at 40MHz ÓInfluence of MEMORY switching on DLL not tested ÓInfluence of test chip specific MUX on DLL Guard Ring cut DNL [Bin]

10 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 10 OTIS MEMORY ÓImplemented on OTIS MEM1.0 ÓDual Ported Memory Ó240 bit total Pipeline Width Ó164 rows long ÓRadiation hard layout ÓLow power design

11 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 11 MEMORY Timing SymbolParameterSimulationTest chipUnit BestWorstBestWorst t AVRH address valid to read enable high ns t RLAX read enable low to address transition ns t RHRL read enable high to read enable low ns t RLRH read enable low to read enable high ns t RLDX read enable low to data transition=1=2=1.3=1.6ns t RLDV read enable low to data valid=3.5=7=4.7=5.1ns t DVWL data valid to write enable low ns t WLDX write enable low to data transition ns t AVWL address valid to write enable low ns t WLAX write enable low to address transition ns t WHWL write enable high to write enable low ns t WLWH write enable low to write enable high 8 16 x <5ns

12 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 12 OTIS CONTROL ALGORITHM ÓImplementation of control elements in Verilog exists ÓSimulation of: ÓVerilog Code exists ÓFPGA Code exists ÓTests on FPGA are running The FPGA is used for verification of the OTIS CONTROL ALGORITHM.

13 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 13 Implemented Elements ÓBunch crossing Counter ÓPipeline Control ÓCopy to Derandomizing Buffer ÓDerandomizing Buffer Control ÓReadout Control Ó1, 2, 3 Bunch crossings per Trigger ÓOptional Bunch crossing Reuse ÓTrigger Counter Simulation and Synthesis for FPGA and ASIC

14 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 14 Summary ÓOTISDLL1.0 ÓLock Range Mhz ÓClock, Hit Signalsdifferential ÓDNL0.79 ÓProblems: cross talk from MUX Guard Ring cut needed ÓMEMORY ÓFunctional Testsuccessful ÓTimingwithin specification ÓCONTROL ALGORITHM ÓLogic synthesizable for FPGA and ASIC ÓTests on FPGA are in progress

15 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 15 Next steps ÓDLL: ÓSimultaneous operation of MEMORY and DLL (Power consumption, cross talk DNL etc.) ÓGuard-Ring cut to reduce noise from MUX ÓDerandomizing Buffer: ÓTiming (Beetle SR Test chip) ÓCONTROL ALGORITHM: ÓOngoing tests with FPGA ÓDesign for Test: Memory Self test Implementation of external memory access ÓFast serial link via GOL-chip

16 Harald Deppe, Martin Feuerstack-Raible, Andre Srowig, Uwe Stange, Ulrich Trunk, Dirk WiednerHeidelberg University 16 Future Steps ÓSpecification until October 2001 ÓSubmission of first complete OTIS prototype in February 2002


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