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1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 1 From Zero to One.

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1 1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 1 From Zero to One

2 2 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.1 Levels of abstraction for an electronic computing system (Image by Euroarms Italia )www.euroarms.net

3 3 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.2 Flintlock rifle with a close-up view of the lock

4 4 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.3 Babbages Analytical Engine, under construction at the time of his death in 1871 (image courtesy of Science Museum/Science and Society Picture Library)

5 5 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.4 Representation of a decimal number

6 6 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.5 Conversion of a binary number to decimal

7 7 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.6 Conversion of a hexadecimal number to decimal

8 8 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.7 Least and most significant bits and bytes

9 9 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.8 Addition examples showing carries: (a) decimal (b) binary

10 10 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.9 Binary addition example

11 11 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.10 Binary addition example with overflow

12 12 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.11 Number line and 4-bit binary encodings

13 13 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.12 NOT gate

14 14 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.13 Buffer

15 15 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.14 AND gate

16 16 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.15 OR gate

17 17 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.16 More two-input logic gates

18 18 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.17 XNOR gate

19 19 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.18 XNOR truth table

20 20 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.19 Three-input NOR gate

21 21 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.20 Three-input NOR truth table

22 22 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.21 Four-input AND gate

23 23 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.22 Four-input AND truth table

24 24 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.23 Logic levels and noise margins

25 25 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.24 Inverter circuit

26 26 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.25 DC transfer characteristics and logic levels

27 27 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.26 Silicon lattice and dopant atoms

28 28 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.27 The p-n junction diode structure and symbol

29 29 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.28 Capacitor symbol

30 30 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.29 nMOS and pMOS transistors

31 31 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.30 nMOS transistor operation

32 32 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.31 Switch models of MOSFETs

33 33 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.32 NOT gate schematic

34 34 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.33 Two-input NAND gate schematic

35 35 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.34 General form of an inverting logic gate

36 36 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.35 Three-input NAND gate schematic

37 37 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.36 Two-input NOR gate schematic

38 38 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.37 Two-input AND gate schematic

39 39 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.38 Transmission gate

40 40 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.39 Generic pseudo-nMOS gate

41 41 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.40 Pseudo-nMOS four-input NOR gate

42 42 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.41 Three-input majority gate

43 43 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.42 Three-input AND-OR gate

44 44 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.43 Three-input OR-AND-INVERT gate

45 45 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.44 DC transfer characteristics

46 46 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.45 DC transfer characteristics

47 47 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.46 DC transfer characteristics

48 48 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.47 Bens buffer DC transfer characteristics

49 49 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.48 Two-input DC transfer characteristics

50 50 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.49 Two-input DC transfer characteristics

51 51 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.50 Mystery schematic

52 52 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.51 Mystery schematic

53 53 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.52 RTL NOT gate

54 54 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 01

55 55 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 02

56 56 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 03a

57 57 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 03b

58 58 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 04

59 59 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 05

60 60 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 06

61 61 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 07

62 62 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 08

63 63 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 10

64 64 Copyright © 2013 Elsevier Inc. All rights reserved. UNN Figure 1


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