1. TDC130: High performance Time to Digital Converter in 130 nm
Christian MESTER

2. Index Introduction: New TDC130 What is a TDC and its use
Application example
HPTDC implementation
New TDC130
Expected resolution
Current state
Architecture
Focus on DLL
Ideas for further improvement of resolution
Pico-Second Timing Workshop
Chicago, March 2008

3. What is a TDC and its use
TDCs are used to measure time (intervals) with high precision
Start – stop measurement
Measurement of time interval between two events: start signal – stop signal
Used to measure relatively short time intervals with high precision
Like a stop watch used to measure sport competitions
Time tagging
Measure time of occurrence of events with a given time reference Time reference (Clock) Events to be measured (Hit)
Used to measure relative occurrence of many events on a defined time scale
Like a normal watch
Start
Stop
Time scale (clock)
Hits
Pico-Second Timing Workshop
Chicago, March 2008

4. What is a TDC and its use Special needs for high energy physics
Many thousands of channels needed  want to use the same time base for many channels
Rate of measurements can be very high
Very high resolution
Triggered mode must be integrated with TDC function:
store measurements during a given interval
extract only those related to an interesting event, signalled by a trigger
Pico-Second Timing Workshop
Chicago, March 2008

5. ALICE Time of Flight (TOF)
≈ speed of light
particle
≈25 ps resolution
channels
Pico-Second Timing Workshop
Chicago, March 2008

6. Current Implementation (HPTDC)
DLL, hit registers, RC delay and PLL implemented as full custom
0.25 µm CMOS technology
6.5 x 6.5 mm²
≈ 1 million transistors
225 ball grid array package
Pico-Second Timing Workshop
Chicago, March 2008

7. Index Introduction: New TDC130 What is a TDC and its use
Application example
HPTDC implementation
New TDC130
Expected resolution
Current state
Architecture
Focus on DLL
Ideas for further improvement of resolution
Pico-Second Timing Workshop
Chicago, March 2008

8. New TDC130 vs. current HPTDC
≈ 100 ps bin size on 32 channels or ≈ 25 ps bin size on 8 channels
780 ps bin size in low resolution mode
102 µs dynamic range (15 bit)
Max. hit rate on channels depend on other channels’ activity
Double pulse resolution: 5 ns to 10 ns (depending on mode)
New TDC130
≈ 25 ps bin size on 32 channels
≈ 800 ps bin size in low resolution mode
≈ 840 µs dynamic range (20 bit) (possibly more)
Higher hit rates, channels are independent
Minimum double pulse resolution ≤ 2 ns
Lower power consumption
Lower cost
Pico-Second Timing Workshop
Chicago, March 2008

9. TDC130: Current state Timing part To be submitted in May 2008 PLL DLL
Hit registers
24.4 ps bin size in “32” channels
If time allows: additional interpolation function
Pico-Second Timing Workshop
Chicago, March 2008

10. Core architecture of TDC130
32 delay elements+dummies
Clock
(40 MHz, or 80 MHz)
PLL
1.28 GHz
Phase detector, Charge pump, Filter 32
Hit[31:0]
LVDS 32
Hit register
× 32
Readout
Pico-Second Timing Workshop
Chicago, March 2008

11. DLL Timing part Phase detector: bang-bang type
Loop filter: Capacitor to ground
Control voltage for dummies is separated using mirrors not to inject noise on the main elements’ control voltage
Not shown:
Differential to single-ended conversion between delay line and phase detector
Differential to single-ended conversion before hit registers and buffers
Note that the load seen by each delay element has to be the same.
Pico-Second Timing Workshop
Chicago, March 2008

12. DLL: Delay cell Differential delay elements
With local fine adjustment to compensate mismatch effects
This works like an inductor (within a limited frequency range)
Local fine adjustment to compensate for mismatch
Pico-Second Timing Workshop
Chicago, March 2008

13. Monte Carlo Simulation: INL/DNL (TDC130)
25 runs, process variations only
VCDL, differential-to-single-ended converters and buffers
Pico-Second Timing Workshop
Chicago, March 2008

14. Monte Carlo Simulation: INL/DNL (TDC130)
25 runs, mismatch variations only
VCDL, differential-to-single-ended converters and buffers
Pico-Second Timing Workshop
Chicago, March 2008

15. Measurement of HPTDC: INL correction
Effective RMS resolution:
40 ps without INL correction
17 ps with look-up table INL correction (as a fixed 40 MHz pattern has been observed)
Without INL compensation
After INL compensation
Measurements from ALICE-TOF
Pico-Second Timing Workshop
Chicago, March 2008

16. How to improve the resolution?
HPTDC’s very high resolution mode:
Interpolation using R-C delay elements and 4 normal channels per very high resolution channel ( only 8 instead of 32 channels available in very high resolution mode)
TDC130:
Interpolation — without reducing the number of channels?
Ideas:
R-C networks: attenuation, low pass: slew rate deteriorates
Transmission lines: potentially long, less attenuation
Delay elements (like in the DLL)
Use a second DLL with slightly less (e.g. 26) delay elements than the main DLL
Let the clock signal propagate in both DLLs
Distribute the second DLL’s control voltage to delay elements in the channels
Interpolation factor 4  ≈6 ps bin size
Pico-Second Timing Workshop
Chicago, March 2008

17. TDC130: Outlook Final chip Future of the development
General architecture (channel organization, 1 buffer per channel) fixed
Will support triggered mode
Readout: to be discussed
Future of the development
“Client” expectations
“Client” involvement
“Availability” of manpower
“Maintain” expertise
Pico-Second Timing Workshop
Chicago, March 2008