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Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 1 Status of OTIS 1.0 OTIS Review 2003, June 5 OTIS GROUP, Heidelberg University.

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Presentation on theme: "Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 1 Status of OTIS 1.0 OTIS Review 2003, June 5 OTIS GROUP, Heidelberg University."— Presentation transcript:

1 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 1 Status of OTIS 1.0 OTIS Review 2003, June 5 OTIS GROUP, Heidelberg University

2 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 2 OTIS TDC Chip Components: 32 maskable channels (LVDS Input) DLL, HitRegister, PrePipeline: 6 bit drift time encoding: 1 bit 0.39 ns (req. resolut. < 1ns) playback mode for testdata feed-in Pipeline, Derandomizing Buffer: buffer length: 160 evts 4.0 μs Control Algorithm: Memory and trigger management, 2 read-out modes: 1, 2, 3 BX/evt I2C Slow Control Interface: Programming, ASD bias setting DAC: ASD-Chip bias

3 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 3 OTIS TDC Ó3.250 OTIS-TDCs with 32 channels each Ó4 OTIS TDCs are connected to one GOL (fast serializer chip) one fibre per 128 channels ÓRadiation hard layout 0.25 µm CMOS ÓDLL fine time resolution 6 bit ÓDual Ported Memory with 1.2 Gb/s, 240 bit width (low power design) ÓSynchronous clock driven readout

4 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 4 D elay L ocked L oop Test chips for DLL,DLL with MUX and MEMORY : OTISDLL1.0 (Sept. 2000) OTISMEM1.0 (Feb. 2001) 1 st DLL prototype, contains: Delay chain with 32 stages 1 taps each Mean delay per tap 25ns/32 = 780 ps Hit Register for only one channel 2 nd DLL prototype, contains: Delay chain with 32 stages 2 taps each Mean delay per tap 25ns/64 = 390 ps Hit Register for only one channel with 64 bit multiplexed to 4 pads

5 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 5 DLL Lock Time (2nd prototype) Lock Time is below 1µs DLL Out Clock In Phase Difference Control Voltage DLL

6 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 6 DLL Temperature Range (2nd prototype) Measurement of Temperature Range Control Voltage inside Dynamic Range for all tested Temperatures at 40 MHz Vctrl/mV Dynamit Range

7 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 7 Measurements on OTIS 1.0 DLL Lock Range DLL Lock –Time FineTime Measurements Differential Non-Linearity ALL limitations on the functionality of OTIS 1.0 concerning Finetime and HitBit encoding are due to parasitics.

8 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 8 DLL Lock Time (OTIS 1.0) Lock Time is below 1µs DLL Out notReset Control Voltage

9 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 9 DLL Lock Range (OTIS 1.0) Lock Range = 25…60MHz at 300K Spec is 30…50MHz at 300K OK !!! Dynamic Range of Control Voltage 1.4V Dynamic Range

10 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 10 Fimetime Measurements (1) Finetime Measurements for OTIS 1.0

11 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 11 Finetime Measurements (2) Finetime Measurements for an FIB patched OTIS 1.0

12 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 12 Differential Non Linearity (1) Differential Non-Linearity OTIS 1.0 (preliminary): DNL = 1.39 bin (= 0.54ns)

13 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 13 Differential Non Linearity (2) Differential Non-Linearity (corrected with Simulation results): DNL = bin (= ps)

14 Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich UwerHeidelberg University 14 Summary OTIS 1.0 (TDC core) Clock, Hit Signalsdifferential Lock Range MHz Lock Time< 1us DNL1.39 Bins (preliminary measurements), 0.64 Bins (corrected by simulation results), further investigation necessary!! Chan. To Chan. Variation< 1LSB (measured for 1 st BX half) Known Bugs: Drift time encoding for 2 nd BX half and loss of HitBit information! Well understood!!! Signal routing and driver strength have to be improved. A more relaxed timing will be chosen for PrePipe-Components.


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