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R. CORNAT - LPC - LECC Colmar - septembre 2002 1 Level 0 trigger decision unit for the LHCb experiment Rémi CORNAT, Régis LEFEVRE, Jacques LECOQ, Pascal.

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Presentation on theme: "R. CORNAT - LPC - LECC Colmar - septembre 2002 1 Level 0 trigger decision unit for the LHCb experiment Rémi CORNAT, Régis LEFEVRE, Jacques LECOQ, Pascal."— Presentation transcript:

1 R. CORNAT - LPC - LECC Colmar - septembre Level 0 trigger decision unit for the LHCb experiment Rémi CORNAT, Régis LEFEVRE, Jacques LECOQ, Pascal PERRET LPC Clermont-Ferrand

2 R. CORNAT - LPC - LECC Colmar - septembre Outline Introduction I/O General architecture Algorithms (prototype) Prototype Test bench

3 R. CORNAT - LPC - LECC Colmar - septembre L0DU Provides the final L0 trigger decision Decision based on L0 trigger processor (E/HCAL, MUON) RS can apply a veto Decision fan-out by TTC system

4 R. CORNAT - LPC - LECC Colmar - septembre L0DU input/output Calorimeters : MHz MUON : MHz VETO : MHz Total : MHz (2.5 Go/s) RSDA : MHz (to Readout Supervisor) L0Block : MHz MHz to L1) Standard data word - 32 bits - 8b BCID - 8b energy

5 R. CORNAT - LPC - LECC Colmar - septembre Timing Fully synchronous Events sorted in time order Each data source have a fixed latency Not precisely known Minimum latency of L0DU : 275 ns Includes output drivers and cables Additional latency : 250 ns Advanced algorithms 525 ns

6 R. CORNAT - LPC - LECC Colmar - septembre L0DU logical architecture

7 R. CORNAT - LPC - LECC Colmar - septembre RSDA Decision word sent to Readout Supervisor 1b decision 12b BCID (provided by TTC) 1b ask for forced trigger (calibration) 1b timing trigger bit (time alignment) Timing trigger bit set to '1' when Positive decision for BC #N No trigger for BC N-1, N-2, N+1, N+2 No functional errors

8 R. CORNAT - LPC - LECC Colmar - septembre L0Block 32 words of 32 bits Sent one by one for each L0 trigger Words sent one by one at 40 MHz Information for L1 trigger L0DU I/Os Decision history Intermediate results

9 R. CORNAT - LPC - LECC Colmar - septembre L0DU physical architecture A lot of point to point connections External Internal Use of fpga High density (I/O pins, logic cells, internal memory) to limit connection issues BGA type package Integrated LVDS,... I/O buffers Single PCB (no internal connectors and cables if possible) Do not need a crate APEX Virtex

10 R. CORNAT - LPC - LECC Colmar - septembre Input/output format Use of standard connectors and cables Ethernet CAT5+, RJ45 Input : serial LVDS (48 bits on 9 pairs or 21 bits on 4 pairs) for < 20 m links DS90LV483/4 (National Semiconductor) Up to 672 Gbyte/s Pre-emphasis feature DC balancing Tested at LAL (Orsay, France) Output : 40 MHz LVDS

11 R. CORNAT - LPC - LECC Colmar - septembre Algorithms (examples) 3 highest muon search (out of 8) 3 clock cycles, comparator tree Thresholds Invariant mass (muons) Combination between simple conditions Downscaling : temporally relaxed conditions Rate division Acceptation %

12 R. CORNAT - LPC - LECC Colmar - septembre First prototype No ECS, no TTC I/O format : 40 MHz LVDS 96 inputs bits, 32 outputs bits 5 ACEX1K100 (Altera) Simple but exhaustive algorithms Synchronization Trigger conditions Downscaling L0Block building (internal memory)

13 R. CORNAT - LPC - LECC Colmar - septembre First prototype (2) 5 fpgas LVDS I/O RJ45 connectors PCB : 24.5x23.3 cm

14 R. CORNAT - LPC - LECC Colmar - septembre First prototype architecture 1,2 : partial data processing 3 : final processing and decision 4 : storage 5 : L0Block - 3 configuration jumpers per fpga - few spare I/O

15 R. CORNAT - LPC - LECC Colmar - septembre L0block Use of internal memory pipe-line then fifo if trigger multiplexing controlled by comb. Logic and fsm

16 R. CORNAT - LPC - LECC Colmar - septembre Prototype input data L0 wordNotationSynchronisation Primary vertex vetoveFirst available word Highest electronel11 BC after ve Highest hadronh111 BC after ve Second highest hadronh211 BC after ve Calorimeter veto Et 11 BC after ve Highest muonmu15 BC after ve L0 word(s)Encoding ve 6 bits for BCID 2 bits for error 8 bits for multiplicity el, h1 and h2 6 bits for BCID 2 bits for error 8 bits for Et Et6 bits for BCID 10 bits for Et mu 6 bits for BCID 2 bits for error 1 bit for charge 7 bits for Pt

17 R. CORNAT - LPC - LECC Colmar - septembre Very simple algorithm (example) L0 decision positive if {[ Et of the highest electron electron threshold ] or [ Et of the highest hadron one hadron threshold ] or [ ( Et of the highest hadron two hadrons first threshold ) and ( Et of the second highest hadron two hadrons second threshold ) ] or [ Pt of the highest muon muon threshold ] } and { primary vertex veto multiplicity primary vertex veto threshold } and { Et of calorimeter veto calorimeter veto threshold }

18 R. CORNAT - LPC - LECC Colmar - septembre Downscaling ConditionDownscaling 0No downscale at all 1One electron trigger with a lower threshold after few electron triggers 2As in 1 but with others downscaled threshold and frequency 3One muon trigger with a lower threshold after few muon triggers 4 One trigger with lower threshold(s) after few corresponding triggers for electron, one hadron, two hadrons and muon channels 5 Normal electron triggers A part of electron triggers with a lower threshold 6 Normal muon triggers A part of muon triggers with a lower threshold 7 One trigger with lower threshold(s) after few corresponding triggers for one hadron, two hadrons and muon channels Normal electron triggers A part of electron triggers with a lower threshold

19 R. CORNAT - LPC - LECC Colmar - septembre L0DU Report BitSignificationBitSignification 0L0 decision 1Electron trigger2Downscaled electron trigger 3One hadron trigger4Downscaled one hadron trigger 5Two hadrons trigger6Downscaled two hadrons trigger 7Muon trigger8Downscaled muon trigger 9Forced trigger L0DU Initialisation: L0 Data partially lost 13Synchronisation error on L0 Data14Error on L0 Data 15 L0 Block warning: FIFO line 12 (max =16)

20 R. CORNAT - LPC - LECC Colmar - septembre RSDA Sent 9 BC after reception of last L0 Data word Available at Readout Supervisor input after 10 BC See timing of RSDA computation Bit(s)Signification 0L0 decision 1 to 12BCID on 12 bits (6+6) 13Forced trigger 14Timing trigger bit (BC-2, BC-1, BC, BC +1, BC+2) 15 L0 Block warning: FIFO line 12 (max=16)

21 R. CORNAT - LPC - LECC Colmar - septembre L0 Block Ready when RSDA is ready: 40 BC before L0 Trigger Word(s)SignificationWord(s)Signification 0Header: downscaling condition16L0DU Report (BC) 1BCID on 12 bits (6+6)17L0DU Report (BC+1) 2h1 on 10 bits: no BCID18L0DU Report (BC+2) 3h2 on 10 bits: no BCID19 Et(BC-2) Et(BC-1) 4 Et on 10 bits: no BCID 20 Et(BC+1) Et(BC+2) 5ve on 10 bits: no BCID21Normal trigger counter 6mu on 10 bits: no BCID22Downscaled trigger counter 7el on 10 bits: no BCID23Forced trigger counter 8Max Et (h1,h2,mu,el)24Counter of synchronisation error on L0 Data 9 to 13-25Counter of error on L0 Data 14L0DU Report (BC-2)26Counter of L0 Block warning 15L0DU Report (BC-1)27 to 31- ECS

22 R. CORNAT - LPC - LECC Colmar - septembre Test bench Need to synchronize : clock board Fan-out of LVDS and ECL clock signals (10-60 MHz) Manual « start » signal Need to stimulate : memory board bits 40 MHz LVDS words VME controlled C++ software (C++/PVSS software foreseen) Connections : Ethernet CAT5+ and RJ45

23 R. CORNAT - LPC - LECC Colmar - septembre Test bench (2)

24 R. CORNAT - LPC - LECC Colmar - septembre Memory board 16 RJ45 VME interface 4 RAMs 64 LVDS reversible I/O PCB : 24x23.3 cm

25 R. CORNAT - LPC - LECC Colmar - septembre Functionalities Parameters Start and end addresses Number of runs Pipe-line delay External synchronisation signal Many boards in parallel Software in C (LabView version also exists) Electrical format conversion modules can be added

26 R. CORNAT - LPC - LECC Colmar - septembre Conclusion First prototyping successful Emphasis on test bench Embedded test bench foreseen Second prototype (Q1'2004) ECS TTC Up-market fpga


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