Combinatorial Logic Circuits

Combinatorial Logic Circuits
EE141 Combinatorial Logic Circuits EE141

Basic CMOS gates: Properties Ratioed Logic Pass transistor Logic
Index Basic CMOS gates: Properties Ratioed Logic Pass transistor Logic Dynamic Logic EE141

Combinational vs. Sequential Logic
EE141 Combinational vs. Sequential Logic Combinational Logic Circuit Out In State Combinational Sequential Output = f ( In ) Output = f ( In, Previous In ) EE141

At every point in time (except during the switching
Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD or ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. EE141

Static Complementary CMOS
EE141 Static Complementary CMOS VDD F(In1,In2,…InN)=1 produce F=Vdd In1 In2 PUN … PMOS only InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN One and only one of the networks (PUN or PDN) is conducting in steady state F(In1,In2,…InN)=0 produce F=GND PUN and PDN are dual logic networks EE141

NMOS Transistors in Series/Parallel Connection
EE141 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high EE141

PMOS Transistors in Series/Parallel Connection
EE141 PMOS Transistors in Series/Parallel Connection EE141

Complementary CMOS Logic Style
EE141 Complementary CMOS Logic Style EE141

EE141 Example Gate: NAND EE141

EE141 Example Gate: NOR EE141

Complex CMOS Gate B C A D OUT = D + A • (B + C) A D B C EE141
Shown synthesis of pull up from pull down structure D B C EE141

Constructing a Complex Gate
EE141 Constructing a Complex Gate C (a) pull-down network SN1 SN4 SN2 SN3 D F A B (b) Deriving the pull-up network hierarchically by identifying sub-nets V DD (c) complete gate EE141

Standard Cells Datapath Cells Cell Design General purpose logic
EE141 Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width EE141

Standard Cell Layout Methodology – 1980s
EE141 Standard Cell Layout Methodology – 1980s Routing channel VDD signals Contacts and wells not shown. What does this implement?? GND

Standard Cell Layout Methodology – 1990s
EE141 Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 Contacts and wells not shown. What does this implement?? M3 GND Mirrored Cell GND

Standard Cells Cell height 12 metal tracks
EE141 Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” V DD Out In 2 Rails ~10 GND Cell boundary

EE141 Standard Cells 2-input ??? gate V DD A B Out GND

Stick Diagrams Contains no dimensions
EE141 Stick Diagrams Contains no dimensions Represents relative positions of transistors V DD V DD Inverter NAND2 Out Out In A B GND GND

Stick Diagrams Logic Graph j VDD X i GND A B C PUN PDN A j C B
EE141 Stick Diagrams Logic Graph j VDD X i GND A B C PUN PDN A j C B X = C • (A + B) C i Systematic approach to derive order of input signal wires so gate can be laid out to minimize area Note PUN and PDN are duals (parallel <-> series) Vertices are nodes (signals) of circuit, VDD, X, GND and edges are transitions A B A B C EE141

Two Versions of C • (A + B)
EE141 Two Versions of C • (A + B) A C B A B C VDD VDD X X GND GND Line of diffusion layout – abutting source-drain connections Note crossover eliminated by A B C ordering Permutation of input signals that produce uninterrupted active strips is important !

Step 1: Construction of logic graph
EE141 Euler Paths There is a systematic approach to uninterrupted strips of active. Two steps: Step 1: Construction of logic graph Step 2: Identification of Euler graphs Euler path is a path through all nodes such that every edge is visited once. Euler path is equivalent to an uninterrupted A-strip (succesive S and D connections) Consistency: Same ordering for PUN and PDN A path through all nodes in the graph such that each edge is visited once and only once. The sequence of signals on the path is the signal ordering for the inputs. PUN and PDN Euler paths are (must be) consistent (same sequence) If you can define a Euler path then you can generate a layout with no diffusion breaks A B C C A B B C A  no PDN B A C A C B -> no PDN C B A EE141

Euler Path X C i VDD X B A j A B C GND Node Edge = Transistor EE141
A path through all nodes in the graph such that each edge is visited once and only once. The sequence of signals on the path is the signal ordering for the inputs. PUN and PDN Euler paths are (must be) consistent (same sequence) If you can define a Euler path then you can generate a layout with no diffusion breaks A B C C A B B C A  no PDN B A C A C B -> no PDN C B A Edge = Transistor A B C GND EE141

OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B
EE141 OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D EE141

EE141 Example: x = ab+cd EE141

Static Properties of gates Delay characteristics
EE141 CMOS Gates Static Properties of gates Delay characteristics Fan-in and Fan-out considerations EE141

Depend on input pattern
Static Properties Depend on input pattern 0V 3V Vin Vout a) A=B=0 → 1 b) A=1, B=0 → 1 c) B=1, A=0 → 1 Two pull-up transistors in parallel are more difficult to turn off than one One pull-up transistor, one pull-down. Dynamically, the internal node has to be discharged (slower) Vds1 produces bulk effect during discharge. More Vin is needed EE141

Switch Delay Model Req A A B Rp A Rn CL Cint CL B Rn A Rp Cint A Rp A
EE141 Switch Delay Model Req A A B Rp A Rn CL Cint CL B Rn A Rp Cint A Rp A Rp A Rn CL Note capacitance on the internal node – due to the source grain of the two fets in series and the overlap gate capacitances of the two fets in series NOR2 INV NAND2 EE141

Input Pattern Effects on Delay
EE141 Input Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 Rp/2 CL one input goes low delay is 0.69 Rp CL when N transistor A goes off, internal node has to be charged High to low transition both inputs go high delay is Rn CL A Rp B Rp CL Rn B A Rn Cint EE141

Delay Dependence on Input Patterns
EE141 Delay Dependence on Input Patterns Input Data Pattern Delay (psec) A=B=01 67 A=1, B=01 64 A= 01, B=1 61 A=B=10 45 A=1, B=10 80 A= 10, B=1 81 A=B=10 A=1 0, B=1 A=1, B=10 Voltage [V] Gate sizing should result in approximately equal worst case rise and fall times. Reason for difference in the last two delays is due to internal node capacitance of the pulldown stack. When A transitions, the pullup only has to charge CL; when A=1 and B transitions pullup have to charge up both CL and Cint. For high to low transitions (first three cases) delay depends on state of internal node. Worst case happens when internal node is charged up to VDD – VTn. Conclusions: Estimates of delay can be fairly complex – have to consider internal node capacitances and the data patterns. time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF when N transistor A goes off, internal node has to be charged (slower) EE141

NAND based implementations are preferred over NOR …
EE141 Transistor Sizing CL B Rn A Rp Cint B Rp A Rn CL Cint 4 2 2 1 Assumes Rp = Rn NAND based implementations are preferred over NOR … EE141

Transistor Sizing a Complex CMOS Gate
EE141 Transistor Sizing a Complex CMOS Gate A B 8 6 4 3 C 8 6 D 4 6 OUT = D + A • (B + C) For class lecture. Red sizing assuming Rp = Rn Follow short path first; note PMOS for C and B 4 rather than 3 – average in pull-up chain of three – (4+4+2)/3 = 3 Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where Rn = 3 Rp) Sizing rules of thumb PMOS = 3 * NMOS 1 in series = 1 2 in series = 2 3 in series = 3 etc. A 2 D 1 B 2 C 2 EE141

Fan-In Considerations
EE141 Fan-In Considerations A B C D Distributed RC model (Elmore delay) tpHL = 0.69 Re (C1+2C2+3C3+4CL) = Re C1+2 Re C2+3Re C3+4Re CL * Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. (prop. to R×C) * Internal nodes important !! CL A C3 B C2 C While output capacitance makes full swing transition (from VDD to 0), internal nodes only transition from VDD-VTn to GND C1, C2, C3 on the order of 0.85 fF for W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS CL of 3.2 fF with no output load (all diffusion capacitance – intrinsic capacitance of the gate itself). To give a 80.3 psec tpHL (simulated as 86 psec) C1 D EE141

tp as a Function of Fan-In
EE141 tp as a Function of Fan-In Intrinsec C increases linearly Series transistors cause a double slowdown Parallel transistors increase C quadratic tp (psec) tpHL tp tpLH Fixed fan-out (NMOS 0.5 micrcon, PMOS 1.5 micron) tpLH increases linearly due to the linearly increasing value of the diffusion capacitance tpHL increase quadratically due to the simultaneous incrase in pull-down resistance and internal capacitance linear fan-in Gates with a fan-in greater than 4 should be avoided. EE141

tp as a Function of Fan-Out
EE141 tp as a Function of Fan-Out All gates have the same drive current. tpNOR2 tpNAND2 tpINV tp (psec) Slope is a function of “driving strength” slope is a function of the driving strength eff. fan-out EE141

tp as a Function of Fan-In and Fan-Out
EE141 tp as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO a1 term is for parallel chain, a2 term is for serial chain, a3 is fan-out EE141

Fast Complex Gates: Design Technique 1
EE141 Fast Complex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Lower caps see smaller R CL InN MN C3 In3 M3 M1 have to carry the discharge current from M2, M3, … MN and CL so make it the largest MN only has to discharge the current from MN (no internal capacitances) C2 In2 M2 C1 In1 M1 Can reduce delay by more than 20%; decreasing gains as technology shrinks EE141

EE141 Fast Complex Gates: Design Technique 2 Transistor ordering Transistor with more activity or with latest changes on top critical path critical path 01 CL CL charged charged 1 In1 In3 M3 M3 1 C2 1 C2 In2 In2 M2 discharged M2 charged For lecture. Critical input is latest arriving signal Place latest arriving signal (critical path) closest to the output 1 C1 C1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL EE141

EE141 Fast Complex Gates: Design Technique 3 Alternative logic structures F = ABCDEFGH Reduced fan-in -> deeper logic depth Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate (second configuration). Only simulation will tell which of the last two configurations is faster, lower power There are techniques to minimize switching time: logical effort EE141

EE141 Fast Complex Gates: Design Technique 4 Isolating fan-in from fan-out using buffer insertion CL CL Reduce CL on large fan-in gates, especially for large CL, and size the inverters progressively to handle the CL more effectively EE141

EE141 Fast Complex Gates: Design Technique 5 Reducing the voltage swing linear reduction in delay (only when variation of Req is not substantial; after this, delay gets worse) also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) tpHL = 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn ) EE141

Stages with general logic
What happens in the general case: no longer inverters Suppose we drive a load using a non-inverter stage We increase the transistors by a factor g so that we have the same driving as the inverter (per input) The input capacitance is g times bigger there’s more than one input EE141 tpo is the intrinsic time of a min. size inv.

Logical Effort f – effective fanout
EE141 Logical Effort f – effective fanout p – intrinsic delay factor (multiple times of the inverter intrinsic delay) g – logical effort (ratio of its input capacitance to the inverter capacitance when sized to deliver the same current). Increases with gate complexity. Depends only on topology EE141

EE141 Logical Effort Logical effort quantifies how much less driving strength a gate has compared to an inveter B A F V DD 1 2 4 Inverter 2-input NAND 2-input NOR g = 1 g = 4/3 g = 5/3 EE141

Intrinsic delay factors
Gate Type P Inverter 1 N-input NAND N N-input NOR N-way mux 2 N XOR, NXOR N 2^(N-1) EE141

Logical Effort of Gates
EE141 Logical Effort of Gates t pNAND g = 4/3 p = 2 d = (4/3)h+2 pINV t Normalized delay (d) g = 1 p = 1 d = h+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h) EE141

Logical Effort of Gates
2-input NAND: p=2; g=4/3 Inverter: P=1; g=1 5 4 3 Effort Delay 2 Normalized Delay 1 Intrinsic Delay 1 2 3 4 5 Fanout f EE141

Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN
EE141 Multistage Networks Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN Branching effort: B = b1b2…bN Path effort: H = GFB Path delay EE141

EE141 Add Branching Effort Branching effort: EE141

Optimum Effort per Stage
EE141 Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: EE141

The others are obtained iteratively
Sizing After the fi’s have been obtained, the sizing factors si’s are calculated starting from the first one: The others are obtained iteratively Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999. EE141

Example: Optimize Path
EE141 Example: Optimize Path 1 a b c 5 g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c EE141

EE141 Example – 8-input AND EE141

EE141 Summary Sutherland, Sproull Harris EE141

Ratioed Logic EE141

EE141 Ratioed Logic EE141

EE141 Active Loads EE141

EE141 Pseudo-NMOS EE141

EE141 Pseudo-NMOS VTC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V in [V] o u t W/L p = 4 = 2 = 1 = 0.25 = 0.5 The bigger P, the fastest the L to H transition, but more power and higher Vol i VOL V’OL v EE141

Performance of a P-NMOS inverter
Size Vol Static P Tplh 4 0.693 564W 14 ps 2 0.273 298 W 56 ps 1 0.133 160 W 123 ps 0.064 80 W 268 ps 1/4 0.031 41 W 569 ps EE141

Differential Cascode Voltage Switch Logic (DCVSL)
EE141 Improved Loads (2) V V DD DD M1 M2 Out Out A A PDN1 PDN2 B B V V SS SS Differential Cascode Voltage Switch Logic (DCVSL) EE141

DCVSL Transient Response
EE141 DCVSL Transient Response 0.2 0.4 0.6 0.8 1.0 -0.5 0.5 1.5 2.5 A B A B A B [V] e A B g a t l o A , B V A,B Time [ns] EE141

Pass-Transistor Logic
EE141

Pass-Transistor Logic
EE141 Pass-Transistor Logic EE141

B A F = AB Example: AND Gate Bottom ensures low impedance path
EE141 Example: AND Gate Bottom ensures low impedance path B=1 and A=1 produces a weak 1 ouput Worsened by body effect Fewer gates Smaller capacitance B A F = AB EE141

EE141 NMOS-Only Logic 3.0 In Out [V] 2.0 x e g a l t o V 1.0 0.0 0.5 1 1.5 2 Time [ns] Tail end of transient very slow due to the small current available EE141

Series cascade EE141

NMOS-only Switch Vb does not pull up to 2.5V, but to 2.5V - Vtn
EE141 NMOS-only Switch A = 2.5 V B C = 2.5 V C L M 2 1 n Vb does not pull up to 2.5V, but to 2.5V - Vtn Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) EE141

NMOS Only Logic: Level Restoring Transistor
EE141 NMOS Only Logic: Level Restoring Transistor V DD V Level Restorer DD M r B M 2 X A M n Out M 1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem: Mn has to be able to pull down node X from Vdd to GND EE141

Restorer Sizing Upper limit on restorer size
EE141 Restorer Sizing 100 200 300 400 500 0.0 1.0 2.0 W / L r =1.0/0.25 =1.25/0.25 =1.50/0.25 =1.75/0.25 V o l t a g e [V] Time [ps] 3.0 Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack Fall time is accelerated, rise is slowed down Transistor Mn is fixed and size of Feedback (Mr) is increased (Switching threshold of inverter is mid-rail). EE141

Solution 2: Single Transistor Pass Gate with VT=0
EE141 Solution 2: Single Transistor Pass Gate with VT=0 V DD V DD 0V 2.5V  V 0V Out DD  2.5V WATCH OUT FOR LEAKAGE CURRENTS EE141

Complementary Pass Transistor Logic
EE141 Complementary Pass Transistor Logic EE141

Complementary Pass Transistor Logic
EE141 Complementary Pass Transistor Logic Complementary data inputs and outputs are always available Output are always connected to low-impedance Design is very modular. The same topology is used. Permutation of inputs is used. Complementary signals have to be routed Restorer has to be used, otherwise static consumption EE141

Solution 3: Transmission Gate
EE141 Solution 3: Transmission Gate C C A B A B C C C = 2.5 V A = 2.5 V B C L C = 0 V EE141

Pass-Transistor Based Multiplexer
EE141 Pass-Transistor Based Multiplexer S S VDD GND In1 S S In2 EE141

EE141 Transmission Gate XOR B B M2 A A F M1 M3/M4 B B EE141

Resistance of Transmission Gate
EE141 Resistance of Transmission Gate R [kΩ] It has a series resistance that can be assumed constant, and equal to a couple of KΩ EE141

Delay in Transmission Gate Networks
EE141 Delay in Transmission Gate Networks V n-1 n C 2.5 In 1 i i+1 V 1 i-1 C 2.5 i i+1 R eq C (a) (b) m R eq R eq R eq In C C C C (c) EE141

EE141 Delay Optimization mopt is typically 3 or 4 .. EE141

Dynamic Logic EE141

EE141 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors EE141

Dynamic Gate Two phase operation Precharge (CLK = 0)
EE141 Dynamic Gate Out Clk A B C Mp Me Clk Mp Out CL In1 In2 PDN In3 Clk Me For class handout Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) EE141

Dynamic Gate Two phase operation Precharge (Clk = 0)
EE141 Dynamic Gate Out Clk A B C Mp Me off Clk Mp on 1 Out CL ((AB)+C) In1 In2 PDN In3 Clk Me off For lecture Evaluate transistor, Me, eliminates static power consumption on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) EE141

Inputs to the gate can make at most one transition during evaluation.
EE141 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails. EE141

Properties of Dynamic Gates
EE141 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL CL being lower also contributes to power savings EE141

Properties of Dynamic Gates
EE141 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities due to periodic charge and discharge extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock EE141

Issues in Dynamic Design: Charge Leakage
EE141 Issues in Dynamic Design: Charge Leakage CLK Clk Mp Out CL A Evaluate VOut Clk Me Precharge leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device. Charge stored on CL will leak away with time (input in low state during evaluation) Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks) PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths. Leakage sources Dominant component is subthreshold current EE141

Solution to Charge Leakage
EE141 Solution to Charge Leakage Keeper Clk Mp Mkp CL A Out B Clk Me During precharge, Out is VDD and inverter out is GND, so keeper is on During evaluation if PDN is off, the keeper compensates for drained charge due to leakage. If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually Note Psc during switching period when PDN and keeper are both on simultaneously Same approach as level restorer for pass-transistor logic EE141

Issues in Dynamic Design: Charge Sharing
EE141 Issues in Dynamic Design: Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out CL A CA B=0 CA initially discharged and CL fully charged. CB Clk Me EE141

Charge Sharing V Clk M Out C A M X C B = M C Clk M EE141 DD p L a a b
M b C b Clk M e EE141

Solution to Charge Redistribution
EE141 Solution to Charge Redistribution Clk Clk Mp Mkp Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) EE141

Issues in Dynamic Design: Backgate Coupling
EE141 Issues in Dynamic Design: Backgate Coupling Clk Mp Out1 =1 Out2 =0 CL1 CL2 In A=0 B=0 Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces Clk Me Dynamic NAND Static NAND EE141

Backgate Coupling Effect
EE141 Backgate Coupling Effect Out1 Voltage Clk Out1 overshoots Vdd (2.5V) due to clock feedthrough And Out2 never quite makes it to GND Out2 In Time, ns EE141

Issues in Dynamic Design 4: Clock Feedthrough
Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Clk Mp Out CL A B Clk Me Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate. Signal levels above VDD may cause the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate: a) possible latch-up, b) other nodes disturbed EE141

Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk In4
Voltage In4 Out Clk Time, ns Clock feedthrough EE141

Minority charge injection Supply noise (ground bounce)
EE141 Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) EE141

Cascading Dynamic Gates
EE141 Cascading Dynamic Gates V Clk Clk Clk Mp Mp Out2 Out1 In In Out1 VTn Clk Clk Me Me Out2 V Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. The second dynamic inverter turns off (PDN) when Out1 reaches VTn. Setting all inputs of the second gate to 0 during precharge will fix it. Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 -> 1 transition during the evaluation period t Due to finite discharge time of first stage, the second stage output drops when it shouldn’t EE141

Domino Logic Clk Clk Out1 Out2 In1 In4 PDN In2 PDN In5 In3 Clk Clk Mp
EE141 Domino Logic Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1 Clk Me Clk Me Output transition always starts at 0, and only 0 →1 transitions occur EE141

Why Domino? Like falling dominos! Ini PDN Inj Ini Inj PDN Ini PDN Inj
EE141 Why Domino? Ini PDN Inj Ini Inj PDN Ini PDN Inj Ini PDN Inj Clk Clk Like falling dominos! EE141

Properties of Domino Logic
EE141 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort First 32 bit micro (BellMAC 32) was designed in Domino logic Now a rather rare design style due to non-inverting logic only EE141

Summary Static CMOS: Performance is a strong function of fan-in. Speed is a linear function of fan-in Ratioed logic: reduction of complexity at the expense of static consumption and asymmetrical response Pass-transistor logic: simple for some functions. Long switch networks have quadratic delay. NMOS only networks are even simpler, but suffer from power consumption and reduced margins Dynamic logic: Trades off noise margins for performance. Sensitive to leakage, coupling and charge sharing. Cascading can cause problems EE141

Appendix I Elmore Delay EE141

EE141 Y. Ismail, Equivalent Elmore Delays for RLC Trees, Proc. DAC 1999

Combinatorial Logic Circuits

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