1. Digital CMOS Logic Circuits1

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Figure Digital IC technologies and logic-circuit families.

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Figure Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

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Figure Definitions of propagation delays and switching times of the logic inverter.

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Figure (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.

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Figure The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched.

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Figure Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving an identical inverter formed by Q3 and Q4.

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Figure Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.

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Figure Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.

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Figure Examples of pull-down networks.

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Figure Examples of pull-up networks.

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Figure Usual and alternative circuit symbols for MOSFETs.

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Figure A two-input CMOS NOR gate.

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Figure A two-input CMOS NAND gate.

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Figure CMOS realization of a complex gate.

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Figure Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10.25). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (10.26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10.27).

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Figure Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.

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Figure Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.

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Figure Circuit for Example 10.2.

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Figure (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter.

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Figure Graphical construction to determine the VTC of the inverter in Fig

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Figure VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5 V, Vtn = –Vtp = 1 V, and r = 9.

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Figure NOR and NAND gates of the pseudo-NMOS type.

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Figure Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).

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Figure Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.

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Figure A basic design requirement of PTL circuits is that every node have, at all times, a low-resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in (b) through switch S2.

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Figure Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for the case with the switch closed (vC is high) and the input going high (vI = VDD).

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Figure Operation of the NMOS switch as the input goes low (vI = 0 V). Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles comparison to the circuit in Fig

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Figure The use of transistor QR, connected in a feedback loop around the CMOS inverter, to restore the VOH level, produced by Q1, to VDD.

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Figure Operation of the transmission gate as a switch in PTL circuits with (a) vI high and (b) vI low.

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Figure Realization of a two-to-one multiplexer using pass-transistor logic.

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Figure Realization of the XOR function using pass-transistor logic.

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Figure An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated.

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Figure (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.

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Figure (a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge-sharing problem at the expense of static power dissipation.

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Figure Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase CL2 will partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction.

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Figure E10.12

38. Figure 10. 36 The Domino CMOS logic gate
Figure The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0-to-1 transition (to VDD).

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Figure (a) Two single-input domino CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase.

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Figure Capture schematic of the CMOS inverter in Example 10.5.

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Figure Input–output voltage transfer characteristic (VTC) of the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.

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Figure (a) Output voltage, and (b) supply current versus input voltage for the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.

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Figure Transient response of the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.

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Figure P10.14

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Figure P10.36

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Figure P10.38

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Figure P10.49

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Figure P10.51