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EE415 VLSI Design COMBINATIONAL LOGIC DYNAMICS [Adapted from Rabaeys Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Presentation on theme: "EE415 VLSI Design COMBINATIONAL LOGIC DYNAMICS [Adapted from Rabaeys Digital Integrated Circuits, ©2002, J. Rabaey et al.]"— Presentation transcript:

1 EE415 VLSI Design COMBINATIONAL LOGIC DYNAMICS [Adapted from Rabaeys Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2 EE415 VLSI Design Fast Complex Gates: Design Technique 1 l Transistor sizing »as long as fan-out capacitance dominates l Progressive sizing In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%;

3 EE415 VLSI Design Fast Complex Gates: Design Technique 2 l Transistor ordering C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path charged charged 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L charged discharged

4 EE415 VLSI Design Fast Complex Gates: Design Technique 3 l Alternative logic structures F = ABCDEFGH

5 EE415 VLSI Design Fast Complex Gates: Design Technique 4 l Isolating fan-in from fan-out using buffer insertion CLCL CLCL

6 EE415 VLSI Design Fast Complex Gates: Design Technique 5 l Reducing the voltage swing »linear reduction in delay »also reduces power consumption l But the following gate is much slower! l Or requires use of sense amplifiers to restore the signal level (memory design) t pHL = 0.69 (3/4 (C L V DD )/ I DSATn ) = 0.69 (3/4 (C L V swing )/ I DSATn )

7 EE415 VLSI Design Sizing Logic Paths for Speed l Frequently, input capacitance of a logic path is constrained l Logic also has to drive some capacitance l Example: ALU load in an Intels microprocessor is 0.5pF l How do we size the ALU datapath to achieve maximum speed? l We have already solved this for the inverter chain – can we generalize it for any type of logic?

8 EE415 VLSI Design Buffer Example For given N: C i+1 /C i = C i /C i-1 To find N: C i+1 /C i ~ 4 How to generalize this to any logic path? CLCL InOut 12N (in units of inv )

9 EE415 VLSI Design Logical Effort p – intrinsic delay (3kR unit C unit ) - gate parameter f(W) g – logical effort (kR unit C unit ) – gate parameter f(W) f – effective fanout Normalize everything to an inverter: g inv =1, p inv = 1 Divide everything by inv (everything is measured in unit delays inv ) Assume = 1.

10 EE415 VLSI Design Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

11 EE415 VLSI Design Logical Effort l Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates l Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current l Logical effort increases with the gate complexity

12 EE415 VLSI Design Intrinsic Delay l Inverter has the smallest intrinsic delay and of all static CMOS gates l Intrinsic delay of a gate presents the ratio of its output capacitance to the inverter output capacitance when sized to deliver the same current l Intrinsic delay increases with the gate complexity

13 EE415 VLSI Design Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g =p= 1 g = 4/3, p=2g = 5/3, p=2

14 EE415 VLSI Design Logical Effort of Gates Fan-out (f) Normalized delay (d) t pINV t pNAND F(Fan-in) g = 1 p = 1 d = f+1 g = 4/3 p = 2 d = (4/3)f+2 h = g f d = h+p g – logical effort f - effective fan out p – intrinsic delay Intrinsic Delay Effort Delay

15 EE415 VLSI Design Add Branching Effort Branching effort:C off-path is the branch capacitance

16 EE415 VLSI Design Multistage Networks Stage effort: h i = g i f i Path electrical effort: F = C out /C in Path logical effort: G = g 1 g 2 …g N Branching effort: B = b 1 b 2 …b N Path effort: H = GFB Path delay D = d i = p i + h i

17 EE415 VLSI Design Optimum Effort per Stage When each stage bears the same effort: Minimum path delay Effective fanout of each stage: Stage efforts: g 1 f 1 = g 2 f 2 = … = g N f N

18 EE415 VLSI Design Logical Effort From Sutherland, Sproull

19 EE415 VLSI Design Example – 8-input AND Logical efforts Intrinsic delays Fan out is not known here g=10/3 g=1 p=8 p=1 g=2 g=5/3 p=4 p=2 g=4/3 g=5/3 g=4/3 g=1 p=2 p=2 p=2 p=1

20 EE415 VLSI Design Example: Optimize Path g 1 = 1 f 1 = ag 2 /g 1 g 2 = 5/3 f 2 = bg 3 /ag 2 g 3 = 5/3 f 3 = cg 4 /bg 3 g 4 = 1 f 4 = 5/cg 4 = Effective fanout, F = 5 Path electrical effort: F = Cout/Cin G = Path logical effort : G = g1g2…gN H = Path effort: H = GFB h =Stage effort: hi = gifi a = b = c = Stage fan-out is f i and a,b,c are scale factors comparing a gate size to the minimum size gate with the same speed as inverter Output load Input load

21 EE415 VLSI Design Example: Optimize Path g 1 = 1 f 1 = ag 2 /g 1 g 2 = 5/3 f 2 = bg 3 /ag 2 g 3 = 5/3 f 3 = cg 4 /bg 3 g 4 = 1 f 4 = 5/cg 4 Effective fanout, F = 5 G = 25/9 H = 125/9 = 13.9 (since no branching here then B=1, H=GFB) h = 1.93(this is the optimum effort for each gate h=H 1/4 ) a = h/g 2 =1.16 (from h=f 1 g 1 =1.93 and f 1 =ag 2 /g 1 ) b = ha/g 3 = 1.34 (same as h=f 2 g 2 =1.93 and f 2 = bg 3 /ag 2 ) c = hb/g 4 = 2.59 (same as h=f 3 g 3 =1.93 and f 3 =cg 4 /bg 3 ) Stage fan-out is f i and a,b,c are scale factors comparing a gate size to the minimum size gate with the same speed as inverter

22 EE415 VLSI Design Method of Logical Effort l Compute the path effort: H = GBF l Find the best number of stages N ~ log 4 H l Compute the stage effort h= H 1/N l Sketch the path with this number of stages l Work from either end, find sizes: C in = C out *g/h Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.

23 EE415 VLSI Design Ratio Based Logic Goal: to reduce the number of devices over complementary CMOS

24 EE415 VLSI Design Ratio Based Logic V DD V SS PDN In F R L Load Resistive N transistors + Load V OH = V DD V OL = R DN R + R L Asymmetrical response Static power consumption t pLH = 0.69 R L C L V DD

25 EE415 VLSI Design Ratio Based Logic Problems Problems with Resistive Load I L = (V DD – V out )/ R L Charging current drops rapidly once V out starts to rise Solution: Use a current source! Available current is independent of voltage Reduces t pLH by 25%

26 EE415 VLSI Design Active Loads

27 EE415 VLSI Design Active Loads Depletion mode NMOS load V GS = 0 I L ~ (k n, load / 2) (|V Tn |) 2 Deviates from ideal current source Channel length modulation Body effect V SB varies with V out reduces |V Tn |, hence I L gets smaller for increasing V out

28 EE415 VLSI Design Active Loads Pseudo-NMOS load No body effect, V SB = 0V V GS = - V DD, higher load current I L = (k p / 2) (V DD - |V Tn |) 2 Larger V GS causes pseudo-NMOS load to leave saturation mode sooner than NMOS

29 EE415 VLSI Design Load Lines of Ratioed Gates

30 EE415 VLSI Design Pseudo-NMOS

31 EE415 VLSI Design Pseudo-NMOS VTC Noise margin low is significantly reduced comparing to CMOS V in [V] V o u t W/L p = 4 W/L p = 2 W/L p = 1 W/L p = 0.25 W/L p = 0.5 NL V in_low V in_high V in_low

32 EE415 VLSI Design Pseudo-NMOS NAND Gate V DD GND Out

33 EE415 VLSI Design Improved Loads (1) For fast low-to- high transition in standby circuits

34 EE415 VLSI Design Improved Loads (2) Differential Cascode Voltage Switch Logic (DCVSL) Have no static current Requires that each gate generates both Out and its complement V DD V SS PDN1 OutV DD V SS PDN2 Out A A B B M1M2

35 EE415 VLSI Design DCVSL Example

36 EE415 VLSI Design DCVSL Transient Response Time [ns] V o l t a g e [V] A B A,B A,B DCVSL transient response of AND/NAND gate

37 EE415 VLSI Design Pass-Transistor Logic

38 EE415 VLSI Design Example: AND Gate

39 EE415 VLSI Design NMOS-Only Logic Time [ns] V o l t a g e [V] x Out In

40 EE415 VLSI Design NMOS-only Switch A =2.5 V B C =2.5 V C L A =2.5 V C =2.5 V B M 2 M 1 M n Threshold voltage loss causes static power consumption V B does not pull up to 2.5V, but 2.5V - V TN NMOS has higher threshold than PMOS (body effect)

41 EE415 VLSI Design Pass-Transistor Logic- Solution 1: Level Restoring Transistor M 2 M 1 M n M r Out A B V DD V Level Restorer weak transistor X Advantages: Full Swing, No static power dissipation Restorer adds capacitance, takes away pull down current at X Ratio problem

42 EE415 VLSI Design Restorer Transistor Sizing W/L r =1.0/0.25 W/L r =1.25/0.25 W/L r =1.50/0.25 W/L r =1.75/0.25 V o l t a g e [V] Time [ps] 3.0 Level restoring transistor cannot be too strong otherwise it will prevent output from reaching VDD value Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack

43 EE415 VLSI Design Pass-Transistor Logic - Solution 2: Single Transistor Pass Gate with V T =0 If pass transistors have V T =0 the output does not require level restorer but there is a leakage current

44 EE415 VLSI Design Complementary Pass Transistor Logic

45 EE415 VLSI Design Pass-Transistor Logic Solution 3: Transmission Gate A B C C A B C C B C L C = 0 V A =2.5 V C =2.5 V

46 EE415 VLSI Design Resistance of Transmission Gate

47 EE415 VLSI Design Transmission Gate Based Multiplexer GND V DD In 1 In 2 SS S S

48 EE415 VLSI Design Transmission Gate Based XOR A B F B A B B M1 M2 M3/M4

49 EE415 VLSI Design Transmission Gate Full Adder Similar delays for sum and carry 24 transistors Propagate signal

50 EE415 VLSI Design Example: Full Adder

51 EE415 VLSI Design A Revised Adder Circuit

52 EE415 VLSI Design Delay in Transmission Gate Networks C R eq R CC R C In m (c)

53 EE415 VLSI Design Delay Optimization


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