5NMOS TG as a D-Latch CLK=1, Q=D CLK=1 →0, Qlast is stored on C2 CLK=0, high impedance state.
6Problems with NMOS TG Q can only rise to VDD-VT Clock feedthrough at Q when CLK goes lowThe output stored in a high-Z stage afterCLK goes low is susceptible to all of the charge lossmechanisms.4. 𝑄 is not available
7CMOS TG as a latch Q can only rise to VDD-VT Clock feed through at Q when CLK goes lowThe output stored in a high-Z stage afterCLK goes low is susceptible to all of the charge lossmechanisms.4. 𝑄 is not available
8CMOS TG with a 𝑄 Q can only rise to VDD-VT Clock feed through at Q when CLK goes lowThe output stored in a high-Z stage afterCLK goes low is susceptible to all of the charge lossmechanisms.4. 𝑄 is not available
9Use feedback to statically hold the logic value when the latch is off (1) We can NOT drive a load from internal Q
10Use feedback to statically hold the logic value when the latch is off (2)
12Problem & Solution 𝐶𝐿𝐾 CLK Problem: If D and Qprev are different: Driver + TG1 will drive Q to a different value while INV2 and NMOS of TG2 will drive Q to QprevSolution: Size the forward path so that it is stronger than the feedback path.
13Adjust VS Knob: χ as defined in EQ. 4.15 Increase (WNLP)/(LNWP)→ Decreased VS.Decrease (WNLP)/( LNWP) → Increased VS.
14Increase WP to adjust VS WN/LN=200nm/200nm WP/LP=200nm/200nmWN/LN=200nm/200nm WP/LP=460nm/200nm
26Dynamic NAND CLK=0 (Pre-Charged Phase) NMOS is OFF. OUT is charged to VDD.CLK=1 (Logic Evaluation Phase)NMOS is ON.If either A or B is GND, OUT=VDD.If A=B=1, OUT=GNDPrecharge Phase is only a small portion of theclock cycle.Disadvantage:All dynamic logic circuits require a clock.
27General Structure of a Dynamic Gate Disadvantage:All dynamic logic circuits require a clock
29Problem of Domino Logic Gates 1. During the precharge phase, the output voltage is high.There is an active path to ground as soon as the foot transistor is turned on.Once an output node has been discharged, it cannot go high until the next prechargephase.
30Solution Define each stage as a dynamic gate plus an inverter. The output of each stage is now 0 during precharge. Therefore all NMOS transistors are off during precharge and can only be turned on during the evaluation phase.Disadvantage: An inverter can not be created!
31Domino Cascaded GatesDuring the pre-charge phase (Φ=0), Y1, Y2 and Y3 are charged to VDD simultaneously.Φ =0 does not have to last very long since all stages are pre-charged simultaneously.Φ has a high duty cycle.Note: There is no direct current from VDD to GND.
36Propagation Delay of Domino Cascaded Gates The propagation delay is determined by:The falling edge of the dynamic blockThe rising edge of the inverterY1,Y2 and Y3 fall like dominos.
37Improve the fall time of a Dynamic Block Design a domino stage with a stronger pull-down.Increase the sizes of NMOS devices.Static InverterDomino GateThe NMOS devices do not have to fightwith the pull up network. So the switchvoltage is lower. (VTN of the NMOS)
38Improve the Rise Time of an Inverter Design a static inverter with strong pull-upIncrease the size of the PMOS device.Decrease WNLP/LNWP → Increased Vs of the inverterStatic InverterDomino Gate
39Logical Effort Comparison 5/32/3 assuming that CLK is does notarrive prior to either A or B
40Dynamic NOR GateThe Dynamic NOR gate is a faster circuit because only one NMOS device is drivenThe pull-down transistors do not fight with the pull-up devices.
41Limitations of Domino Logic Charge SharingVx(initially)=0V*=(Cout)/(Cx+Cout)VDD
42Minimizing the effect of Charge Sharing Using Keepers XThe keepers keep VX at VDD and reducecharge sharing to minimum. The keepertransistor is weak enough (small W/L ratioby using a large L) that when X=VDD→GND.NMOS can prevail over weak PMOS.Disadvantage: large driver requirement of INV
43Enhancement The INV sees a minimum length device. The effective pull-up strength is controlledby the long device.