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Transmission Gate Based Circuits

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Presentation on theme: "Transmission Gate Based Circuits"— Presentation transcript:

1 Transmission Gate Based Circuits

2 Elmore Delay (HO) Dynamic D-Latch Dynamic Logic
Application of Elmore Delay to Mux Design (Ex. 7.4) Logical Effort of CMOS Transmission Gate ( Dynamic D-Latch Dynamic Logic

3 Distributed RC line as a lumped RC Ladder

4 Lumped

5 NMOS TG as a D-Latch CLK=1, Q=D CLK=1 →0, Qlast is stored on C2
CLK=0, high impedance state.

6 Problems with NMOS TG Q can only rise to VDD-VT
Clock feedthrough at Q when CLK goes low The output stored in a high-Z stage after CLK goes low is susceptible to all of the charge loss mechanisms. 4. 𝑄 is not available

7 CMOS TG as a latch Q can only rise to VDD-VT
Clock feed through at Q when CLK goes low The output stored in a high-Z stage after CLK goes low is susceptible to all of the charge loss mechanisms. 4. 𝑄 is not available

8 CMOS TG with a 𝑄 Q can only rise to VDD-VT
Clock feed through at Q when CLK goes low The output stored in a high-Z stage after CLK goes low is susceptible to all of the charge loss mechanisms. 4. 𝑄 is not available

9 Use feedback to statically hold the logic value when the latch is off (1)
We can NOT drive a load from internal Q

10 Use feedback to statically hold the logic value when the latch is off (2)

11 No Feedback when the latch is ON

12 Problem & Solution 𝐶𝐿𝐾 CLK Problem: If D and Qprev are different:
Driver + TG1 will drive Q to a different value while INV2 and NMOS of TG2 will drive Q to Qprev Solution: Size the forward path so that it is stronger than the feedback path.

13 Adjust VS Knob: χ as defined in EQ. 4.15
Increase (WNLP)/(LNWP)→ Decreased VS. Decrease (WNLP)/( LNWP) → Increased VS.

14 Increase WP to adjust VS
WN/LN=200nm/200nm WP/LP=200nm/200nm WN/LN=200nm/200nm WP/LP=460nm/200nm

15 Typical D-Latch Implementation in CMOS

16 Typical D-Latch Implementation in CMOS
CLK=1 1

17 Typical D-Latch Implementation in CMOS
CLK=0 1 Qprev=1

18 Typical D-Latch Implementation in CMOS
𝐶𝐿𝐾 CLK Qnow=0 Qprev=1 1 Optional

19 Typical D-Latch Implementation in CMOS
𝐶𝐿𝐾 CLK Qnow=1 Qprev=0 1 Node X may have difficulty transitioning to 1 until 𝐶𝐿𝐾 is 0. Optional

20 Schematic of a TG Based D latch

21 Simulation of D-Latch

22 Zoom in to a transition

23 Positive Edge D Flip-flop
D is only transmitted to the output on the rising edge of CLK

24 Positive Edge D FF (CLK=0)

25 Positive Edge D FF (CLK=1)

26 Dynamic NAND CLK=0 (Pre-Charged Phase)
NMOS is OFF. OUT is charged to VDD. CLK=1 (Logic Evaluation Phase) NMOS is ON. If either A or B is GND, OUT=VDD. If A=B=1, OUT=GND Precharge Phase is only a small portion of the clock cycle. Disadvantage: All dynamic logic circuits require a clock.

27 General Structure of a Dynamic Gate
Disadvantage: All dynamic logic circuits require a clock

28 Examples Example 7.6 P7.5 (a) P7.5 (b)

29 Problem of Domino Logic Gates
1. During the precharge phase, the output voltage is high. There is an active path to ground as soon as the foot transistor is turned on. Once an output node has been discharged, it cannot go high until the next precharge phase.

30 Solution Define each stage as a dynamic gate plus an inverter.
The output of each stage is now 0 during precharge. Therefore all NMOS transistors are off during precharge and can only be turned on during the evaluation phase. Disadvantage: An inverter can not be created!

31 Domino Cascaded Gates During the pre-charge phase (Φ=0), Y1, Y2 and Y3 are charged to VDD simultaneously. Φ =0 does not have to last very long since all stages are pre-charged simultaneously. Φ has a high duty cycle. Note: There is no direct current from VDD to GND.

32 Exercise X

33 Solution: 1. NMOS network implements 𝑂𝑈𝑇 while X implements OUT.
2. The output of Inverter implements 𝑂𝑈𝑇

34 Implement the expression

35 Solution

36 Propagation Delay of Domino Cascaded Gates
The propagation delay is determined by: The falling edge of the dynamic block The rising edge of the inverter Y1,Y2 and Y3 fall like dominos.

37 Improve the fall time of a Dynamic Block
Design a domino stage with a stronger pull-down. Increase the sizes of NMOS devices. Static Inverter Domino Gate The NMOS devices do not have to fight with the pull up network. So the switch voltage is lower. (VTN of the NMOS)

38 Improve the Rise Time of an Inverter
Design a static inverter with strong pull-up Increase the size of the PMOS device. Decrease WNLP/LNWP → Increased Vs of the inverter Static Inverter Domino Gate

39 Logical Effort Comparison
5/3 2/3 assuming that CLK is does not arrive prior to either A or B

40 Dynamic NOR Gate The Dynamic NOR gate is a faster circuit because only one NMOS device is driven The pull-down transistors do not fight with the pull-up devices.

41 Limitations of Domino Logic
Charge Sharing Vx(initially)=0 V*=(Cout)/(Cx+Cout)VDD

42 Minimizing the effect of Charge Sharing Using Keepers
X The keepers keep VX at VDD and reduce charge sharing to minimum. The keeper transistor is weak enough (small W/L ratio by using a large L) that when X=VDD→GND. NMOS can prevail over weak PMOS. Disadvantage: large driver requirement of INV

43 Enhancement The INV sees a minimum length device.
The effective pull-up strength is controlled by the long device.


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