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1 Digital Fundamentals Chapter 8 Flip-Flops and Related Devices Resource: CYU / CSIE / Yu-Hua Lee / Not made by Engr. Umar Talha,

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Presentation on theme: "1 Digital Fundamentals Chapter 8 Flip-Flops and Related Devices Resource: CYU / CSIE / Yu-Hua Lee / Not made by Engr. Umar Talha,"— Presentation transcript:

1 1 Digital Fundamentals Chapter 8 Flip-Flops and Related Devices Resource: CYU / CSIE / Yu-Hua Lee / E-mail:yuhualee@cyu.edu.tw Not made by Engr. Umar Talha, special thanks to E#ngr. Jahanzeb Ahmed

2 2 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

3 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 3 Figure 8--1 Two versions of SET-RESET (S-R) latches. Open file F08-01 and verify the operation of both latches.

4 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 4 Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b).

5 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 5 Figure 8--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition.

6 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 6 Figure 8--4 Logic symbols for the S-R and S-R latch.

7 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 7 Figure 8--5

8 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 8 Figure 8--6 The S-R latch used to eliminate switch contact bounce.

9 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 9 Figure 8--7 The 74LS279 quad S-R latch.

10 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 10 Figure 8--8 A gated S-R latch.

11 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 11 Figure 8--9

12 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 12 Figure 8--10 A gated D latch.

13 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 13 Figure 8--11

14 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 14 Figure 8--12 The 74LS75 quad gated D latches.

15 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 15 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

16 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 16 Figure 8--13 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered).

17 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 17 Figure 8--14 Operation of a positive edge-triggered S-R flip-flop.

18 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 18 Figure 8--15

19 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 19 Figure 8--16

20 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 20 Figure 8--17 Edge triggering.

21 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 21 Figure 8--18 Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse.

22 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 22 Figure 8--19 Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.

23 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 23 Figure 8--20 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.

24 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 24 Figure 8--21

25 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 25 Figure 8--22 A simplified logic diagram for a positive edge-triggered J-K flip-flop.

26 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 26 Figure 8--23 Transitions illustrating the toggle operation when J =1 and K = 1.

27 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 27 Figure 8--24

28 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 28 Figure 8--25

29 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 29 Figure 8--26 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

30 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 30 Figure 8--27 Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.

31 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 31 Figure 8--28 Open file F08-28 to verify the operation.

32 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 32 Figure 8--29 Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flops.

33 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 33 Figure 8--30 Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flops.

34 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 34 Figure 8--31

35 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 35 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

36 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 36 Figure 8--32 Basic logic diagram for a master-slave J-K flip-flop.

37 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 37 Figure 8--33 Pulse-triggered (master-slave) J-K flip-flop logic symbols.

38 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 38 Figure 8--34

39 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 39 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

40 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 40 8-4 Flip-Flop Operating Characteristics  Propagation Delay Times t PLH t PHL  Set-up Time t s  Hold Time t h  Maximum Clock Frequency f max  Pulse Widths t w  Power Dissipation

41 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 41 Figure 8--35 Propagation delays, clock to output.

42 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 42 Figure 8--36 Propagation delays, preset input to output and clear input to output.

43 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 43 Figure 8--37 Set-up time (t s ). The logic level must be present on the D input for a time equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry.

44 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 44 Figure 8--38 Hold time (t h ). The logic level must remain on the D input for a time equal to or greater than t h after the triggering edge of the clock pulse for reliable data entry.

45 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 45 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

46 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 46 Figure 8--39 Example of flip-flops used in a basic register for parallel data storage.

47 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 47 Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.

48 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 48 Figure 8--41 Example of two J-K flip-flops used to divide the clock frequency by 4. Q A is one-half and Q B is one-fourth the frequency of CLK.

49 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 49 Figure 8--42

50 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 50 Figure 8--43

51 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 51 Figure 8--44 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.

52 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 52 Figure 8--45

53 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 53 Figure 8--46

54 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 54 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

55 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 55 Figure 8--47 A simple one-shot circuit.

56 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 56 Figure 8--48 Basic one-shot logic symbols. CX and RX stand for external components.

57 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 57 Figure 8--49 Nonretriggerable one-shot action.

58 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 58 Figure 8--50 Retriggerable one-shot action.

59 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 59 Figure 8--51 Logic symbols for the 74121 nonretriggerable one-shot.

60 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 60 Figure 8--52 Three ways to set the pulse width of a 74121.

61 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 61 Figure 8--53 Logic symbol for the 74LS122 retriggerable one-shot.

62 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 62 Figure 8--54

63 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 63 Figure 8--55 A sequential timing circuit using three 74LS122 one-shots.

64 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 64 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

65 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 65 Figure 8--56 Internal functional diagram of a 555 timer (pin numbers are in parenthesis).

66 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 66 Figure 8--57 The 555 timer connected as a one-shot.

67 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 67 Figure 8--58 One-shot operation of the 555 timer.

68 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 68 Figure 8--59 The 555 timer connected as an astable multivibrator (oscillator).

69 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 69 Figure 8--60 Operation of the 555 timer in the astable mode.

70 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 70 Figure 8--61 Frequency of oscillation as a function of C 1 and R 1 1 2R 2. The sloped lines are values of R 1 1 2R 2.

71 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 71 Figure 8--62 The addition of diode D 1 allows the duty cycle of the output to be adjusted to less than 50 percent by making R 1, R 2.

72 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 72 Figure 8--63 Open file F08-63 to verify operation.

73 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 73 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

74 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 74 Figure 8--64 Two-phase clock generator with ideal waveforms. Open file F08-64 and verify the operation.

75 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 75 Figure 8--65 Logic analyzer displays for the circuit in Figure 8-64.

76 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 76 Figure 8--66 Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches. Open file F08-66 and verify the operation.

77 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 77 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

78 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 78 Figure 8--67 GAL block diagrams.

79 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 79 Figure 8--68 The GAL22V10 OLMC.

80 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 80 Figure 8--69 The GAL16V8 OLMC.

81 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 81 Combinational Logic Chapter 8 Digital System Application

82 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 82 Figure 8--70 Traffic light control system block diagram.

83 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 83 Figure 8--71 Block diagram of the timing circuits.

84 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 84 Figure 8--72

85 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 85 Figure 8--73

86 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 86 Figure 8--74

87 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 87 Combinational Logic Chapter 8 Problems

88 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 88 Figure 8--75

89 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 89 Figure 8--76

90 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 90 Figure 8--77

91 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 91 Figure 8--78

92 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 92 Figure 8--79

93 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 93 Figure 8--80

94 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 94 Figure 8--81

95 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 95 Figure 8--82

96 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 96 Figure 8--83

97 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 97 Figure 8--84

98 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 98 Figure 8--85

99 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 99 Figure 8--86

100 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 100 Figure 8--87

101 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 101 Figure 8--88

102 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 102 Figure 8--89

103 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 103 Figure 8--90

104 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 104 Figure 8--91

105 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 105 Figure 8--92

106 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 106 Figure 8--93

107 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 107 Figure 8--94

108 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 108 Figure 8--95

109 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 109 Figure 8--96

110 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 110 Figure 8--97

111 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 111 Figure 8--98

112 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 112 Figure 8--99

113 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 113 Figure 8--100

114 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 114 Figure 8--101

115 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 115 Figure 8--102

116 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 116 Figure 8--103

117 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 117 Figure 8--104

118 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 118 Figure 8--105

119 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 119 Figure 8--106

120 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 120 Figure 8--107

121 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 121 Figure 8--108

122 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 122 Figure 8--109

123 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 123 Figure 8--110

124 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 124 Figure 8--111

125 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 125 Figure 8--112

126 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 126 Figure 8--113

127 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 127 Figure 8--114

128 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 128 Figure 8--115

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