Presentation on theme: "Chapter 6 -- Introduction to Sequential Devices. The Sequential Circuit Model Figure 6.1."— Presentation transcript:
Chapter 6 -- Introduction to Sequential Devices
The Sequential Circuit Model Figure 6.1
Models for Sequential Circuits Block diagram representation: Figure 6.1 State Tables and Diagrams: the functional relationship that exists among the input, output, present state, and next state is illustrated by either the state table or the state diagram. The state diagram is a graphical representation of a sequential circuit in which the states are represented by circles and the state transitions (the transfer from the present state y to the next state Y) are shown by arrows. The state table lists the inputs across the top, the outputs along the left side, with the entries in the table being the next state and output for each input and present state.
State Tables and State Diagrams Figure 6.2
Example 6.1 State tables and Diagrams Consider a sequential circuit having one input variable x, two state variables y 1 and y 2, and one output variable z. Inputs: x = 0 x = 1 States: [y 1,y 2 ] =  A [y 1,y 2 ] =  B [y 1,y 2 ] =  C [y 1,y 2 ] =  D Outputs: z = 0 z = 1 The state diagram for this circuit is shown in Fig. 6.3
Example 6.1 (continued) Now assume the circuit is initially in state A. If an input of x = 0 is applied the next state is D and the output is 0. Consider the application of the following input sequence to the circuit x = The circuit will behave as follows: present state: A D B A D B B A C C C input: next state: D B A D B B B A C C C output:
Example sequential circuit State table State diagram Figure 6.3
Memory Devices Memory elements exist indefinitely in one of two possible states, 0 and 1. Binary data are stored in a memory element by placing the element into the 0 state to store a 0 and into the 1 state to store a 1. The output Q of the circuit indicates the present state of the memory. The two memory element types most commonly used in switching circuits are latches and flip-flops. Latches are devices whose excitation inputs control the state of the device. A flip-flop differs from a latch in that it has a control switch called a clock. This means a flip-flop waits for its clock signal before changing states. The final state of a flip-flop is determined by its excitation values at the time the clock signal occurs.
Table 6.1 TTL Memory Elements  Device Elements Element Description Number of 74LS73A LS Negative-edge triggered flip-flop with clear Positive-edge triggered D flip-flop with preset and clear D latch with enable Pulse-triggered JK flip-flop with preset and clear Master-slave JK flip-flop with preset, clear, data lockout 4-Bit hazard-free D latch with clear and dual enable Positive-edge triggered D flip-flop with clear Negative-edge triggered JK flip-flop with preset, clear SR latch with active-low inputs
Set-reset latch S latch redrawnSR latch Traditional view of SR latchLogic symbol of SR latch Figure 6.7
NAND SR Latch Logic diagramStorage mode Reduced logic Logic symbol 1Logic symbol 2 Figure 6.8
SR Latch Timing Diagrams The operation of any latch circuit may be described using a timing diagram. The diagram shown in Fig. 6.9 shows that placing logic 1 signals on both the R and S inputs forces both outputs, Q and Q, to logic 0. When the two inputs are returned to logic 0, a race condition is created, and which state the device will assume can not be determined. Consequently, the use of the SR latch is restricted to exclude the input combination S = R = 1. If the R signal is returned to logic 0 before S, the final state of Q will be a logic 1. If S is returned to logic 0 first, the device will be reset to logic 0.
Set-Reset Latch Timing Diagram Figure 6.9 Ideal (zero-gate delay) Actual timing with non-zero delalys
Delay Parameters Every circuit output requires a nonzero amount of time to respond to changes on its input, as specified by delay parameters t PLH and t PHL. Recall that t PLH designates the delay time between an input change and a corresponding low-to-high transition of an output. t PHL is the delay between an input change and a corresponding high- to-low transition. For a latch circuit the delay parameters represent the sum of the propagation delays through the gates between a given latch input and output, with separate delay parameters usually specified for each input/output pair.
Delay Parameters (continued) For example, Fig illustrates the timing behavior of the SR latch of Fig. 6.7c. Following a change in S from 0 to 1, note that output Q changes from 1 to 0 after propagation delay t PHL through N1. Then the feedback signal causes the Q output to change from 0 to 1 after propagation time t PLH through N2. Thus, output Q always changes before output Q when setting an SR latch built from cross-coupled NOR gates. Therefore, t PHL from input S to output Q involves a single gate delay, whereas t PLH from input S to output Q includes two gate delays.
SR Latch Propagation Delays Figure 6.10
SR Latch Excitation Table and Characteristic Equation The logical operation of the SR latch is summarized in the excitation table of Fig. 6.11a. The excitation table is simply the state table of the latch, showing the state transitions for each combination of excitation inputs. The information from the table can be represented as a state diagram, as shown in Fig. 6.11b, and plotted in K-map form, as shown in Fig. 6.11c, where the value of the next state Q* is plotted as a function of the inputs, S and R, and the present state Q. From the K-map the characteristic equation of the SR latch can be derived: Q* = S + RQ.
SR Latch: Characteristic Equation (continued ) The characteristic equation is so called because it characterizes the operation of the latch. We can classify the latch operation into three cases: 1. S = R = 0 the state does not change 2. S = 1, R = 0 represents the set operation 3. S = 0, R = 1 represents the reset operation
SR latch characteristics Excitation table State diagram K-map of latch output Q* Figure 6.11
Gated SR Latch Often it is desirable to use a special control signal to inhibit state changes in an SR latch while S and R are changing. This device is commonly referred to as a gated SR latch, since the control signal can be thought of as opening a gate through which signals on the S and R inputs propagate to the output. Circuit Structure: In Fig. 6.13a, a control signal C, is added to an SR latch to apply the inputs S and R. The two AND gates apply the control signal S and R during time intervals when the enable signal C is logic 1. When C is logic 0, the inputs are held in the S = R = 0 state.
Gated SR Latch (continued) So the operation of the latch is as follows: when C = 0, no change occurs when C = 1, the SR excitation table of Fig. 6.11a and the characteristic equation describe its function. If the AND gates are changed to NAND gates and cross-coupled NAND gates are used for the SR latch, the circuit of Fig. 6.13b results. The NAND gate implementation of the gated SR latch is shown in Fig. 613.c. The generic logic symbol for the gated SR latch is shown in Fig. 6.13d.
Gated SR Latch With NOR SR latch With NAND SR latch NAND logic diagram (d) logic symbol Figure 6.13
Gated SR Latch (continued) Characteristic Equation: The complete excitation table and state diagram of the gated SR latch are given in Figs. 6.14a and b. From the excitation table the characteristic equation is derived: Q* = SC + RQ + CQ Note that when C = 0 this equation reduces to Q* = Q which means that the present state is held. When C = 1 the equation becomes: Q* = S + RQ, the characteristic equation of the simple SR latch, and thus the latch is enabled.
Gated SR Latch Characteristics Figure 6.14 Excitation table State diagram
Delay Latch When storing data, a memory element’s excitation input is simply the data to be stored. A device (which is called a delay latch or D latch) is needed that transfers a logic value on its excitation input D into the cross-coupled storage cell of a latch. The logic symbol of the D latch is shown in Fig. 6.15a. Such a device can be created from a gated SR latch, by assigning S = D and R = D. The D latch excitation table and state diagram is shown in Figs a and b. A NAND implementation of the D latch is shown in 6.15b and NOR is shown in 6.15c.
Delay Latch (D latch) Logic symbol NAND implementation NOR implementation Figure 6.15
D Latch Characteristics Excitation table State diagram Figure 6.16
D Latch (continued) Characteristic equation: this equation can be derived from that of the gated SR latch by substituting D for S and D for R: Q* = DC + CQ When the enable signal is low, (C = 0), the equation reduces to Q* = Q, meaning the latch is placed in hold mode (no change) operating mode with the latch holding the last value of D that was entered. When the enable signal is high (C = 1), Q* = D, the excitation input D is gated directly to output Q (gated or enabled mode). Fig illustrates the timing diagram for D latch operation.
D Latch Timing Diagram Figure 6.17
D Latch (continued) Timing Constraints : To ensure that a specific value on excitation input D will determine the final state of the latch, D must not be allowed to change too near the time at which the enable signal makes its transition from high to low. Set up time: denoted t su is defined as the period of time immediately preceding the enable signal transition during which the excitation input must be stable. That is, the excitation input must be set up at least t su prior to the enable signal transition and should not change until well after the transition.
D Latch (continued) Hold time : denoted t h is defined as the period of time immediately following the enable signal transition during which D should not change. Therefore, the excitation input must be held constant for at least t h following the enable signal transition to ensure the correct value has been latched. Setup and hold times are illustrated in Fig Note the two constraint violations: - the change in D from 0 to 1 too close to the clock edge represents a setup time violation - the change in D from 1 to 0 too soon after the clock edge may result in an unpredictable state.
D Latch Timing Constraints Figure 6.18
Flip-Flops The latch circuits presented thus far are not appropriate for use in synchronous sequential logic circuits. The possibility of two cascaded combinational circuits feeding each other, generating oscillations and unstable transient behavior can be controlled by using a special timing control signal called a clock. The clock can then be used to restrict the times at which the states of the memory elements may change thus preventing the unstable behavior just described.
Master-Slave SR Flip-Flops One method to prevent unstable behavior is to employ two latches in a master-slave configuration as shown in Fig. 6.21a. When the clock signal C is low, the master latch is in the gated mode and slave is in the hold mode. Changes on the excitation input signal S and R are gated into the master latch while the slave latch ignores any changes on its inputs. When the clock changes to logic 1, the two latches exchange roles. The slave latch enters the gated mode, sending the output of the master latch to the flip-flop output Q, while the master latch enters the hold mode.
Master-Slave SR Flip-Flops (continued) Master-slave flip-flops are sometimes called pulse triggered because they require both logic 0 to 1 and 1 to 0 transitions on the clock input in order to operate properly. The logic symbol of Fig. 6.21b indicates the pulse-triggered nature of the device by showing the clock edge transition that enables the slave at the flip-flop output terminals Q and Q. In Fig. 6.21b, the rising transition indicates that the flip-flop outputs change on the positive edge of a pulse on the clock signal. If the SR flip-flop is used in a synchronous sequential circuit, an unstable oscillation cannot occur because, at all times, either the master or the slave latch is in the hold mode (Fig. 6.21d).
Master-slave SR flip-flop (a) Logic diagram (b) Pulse-triggered device logic symbol Figure 6.21
Master-slave SR flip-flop (continued) ( c) Timing behavior (d) Timing constraints Figure 6.21
Excitation Table and Characteristic Equation The excitation table and state diagram for the SR master-slave flip-flop are presented in Figs. 6.22a and b. Note that the columns S, R, and Q denote the conditions on the flip- flop signals before the clock pulse is applied. The Q* column denotes the flip-flop output after the clock pulse has been applied. The state diagrams of the simple SR latch and the master-slave SR latch are identical. The difference between them is that the latch changes states immediately when S or R changes, whereas all flip-flop state changes are triggered by clock pulses.
SR Master-Slave Flip-Flop Characteristics Q* = S + RQ Figure 6.22
Master-Slave D Flip-Flops A master-slave D flip-flop can be built from two D latches as shown in Fig. 6.23a. This flip-flop operates in the same manner as the SR version; the master latch is gated when the clock is low and the slave, when the clock is high. The logic symbol for this pulse-triggered device indicates that the outputs change on the positive edge of a pulse on the clock signal (Fig. 6.23b). The overall behavior of the D flip-flop output Q can be summarized by noting that Q will assume the value of D on the rising edge of the clock C. Therefore, the characteristic equation for a master-slave D flip-flop is : Q* = D
Master-Slave D Flip-Flop Figure 6.23
Master-slave D flip-flop characteristics Figure 6.24
Master-Slave JK Flip-Flops The JK operates as an SR flip-flop whose inputs are assigned J = S and K = R. However, whereas the S = R = 1 combination is not allowed, the JK uses this special case to incorporate a very useful mode of operation. The additional feature of the JK device is that it state toggles, that is changes from 0 to 1 or from 1 to 0 when J = K = 1. Examination of the state diagram, shown in Fig. 6.25b, indicates that the JK flip-flop will change from the 0 state to the 1 state with an input of J = 1 and K = 0 or J = 1 and K = 1 (toggle). This means that a logic 1 on J will force the device into the 1 condition no matter what value is placed on K. So K is a don’t-care in this case.
Pulse-triggered JK flip-flop characteristics (a) Excitation table (b) State diagram ( c) K-map for Q* Figure 6.25
JK Flip-Flops (continued) By plotting the next state Q* on a K-map, as shown in Fig 6.25c, the characteristic equation of the JK flip-flop can be derived: Q* = KQ + JQ From this equation, the logic diagram for the flip-flop can be derived as presented in Fig. 6.26a. The logic symbol for this device is shown in Fig b. Note that the clock input signal is inverted within the device itself so that the slave will change on the falling edge of the clock.
Pulse-Triggered JK Flip-Flop Realization Figure 6.26 Logic diagram Logic symbol
7476 Dual Pulse-triggered JK Flip-Flop Module Figure 6.27 shows the logic symbol of the SN7476. This device packages two flip-flops that operate in the manner displayed in Fig Included in the configuration are asynchronous set signals PRE and reset signals CLR. The PRE and CLR signals override the operation of the pulse-triggered inputs J, K and CLK. This means that if CLR = 0 then the state Q* goes to 0, or if PRE = 0 the state Q* sets to 1, independent of the values of the clock and the excitation inputs.
The SN7476 Dual Pulse-Triggered JK Flip-Flop Figure 6.27
Edge-triggered D Flip-Flops All the pulse-triggered flip-flops discussed previously, require both a rising and falling edge on the clock for proper operation. Another approach is to design the flip-flop circuitry so that it is sensitive to its excitation inputs only during rising or falling transitions of the clock. A circuit with this design is called positive edge triggered if it responds to a 0 to 1 clock transition, or negative edge triggered if it responds to a 1 to 0 clock transition. The edge-sensitive feature eliminates unstable transients by drastically reducing the period during which the input excitation signals are applied to the internal latches.
7474 Dual Positive-edge-triggered D Flip-Flop Module Fig. 6.28b presents the logic symbol for the SN7474. It is important to note that the small triangle at the C1 input to the device is the standard notation to indicate that it is positive edge triggered. The modes of operation are shown in the excitation table of Fig Note that the asynchronous preset and clear signals override the clocked operation of the circuit. When both CLR and PRE are inactive (high), the clock, CLK, takes control of the device. While CLK is low, the flip-flop is in the hold mode. However, on a 0 to 1 transition of the clock the data input D is transferred to the flip- flop output Q.
SN7474 dual positive-edge-triggered D Flip-Flop (a) Logic diagram (b) generic logic symbol ( c ) IEEE standard logic symbol Figure 6.28
SN7474 Excitation Table Figure 6.29
Edge-triggered Flip-flop Timing Characteristics To ensure proper operation of any edge-triggered flip-flop, the excitation inputs should not change immediately before or after the clock transition. The value of D for the SN7474 is sampled and transferred to the flip- flop output Q at the exact instant the clock reaches its threshold value. One should always make sure that the input is either logic 1 or 0 at this instant in time so that the flip-flop’s output Q will be the value planned in the system design. Fig.6.30
T Flip-flops A common building block used in sequential logic circuits that counts pulses on a signal line is the T flip-flop. The T flip-flop has only one excitation input signal T, as shown on the logic symbol for the device pictured in Fig. 6.33a. The function of this device is to change (toggle) its state upon each negative-going transition of its excitation input signal, as shown in the excitation table and state diagram in Figs. 6.34a and b. Therefore, the characteristic equation of the edge-triggered T flip-flop is simply: Q* = Q
Negative-Edge-Triggered T Flip-Flop Figure 6.33 Logic symbolFunctional equivalent
Edge-Triggered T Flip-Flop Characteristics Figure 6.34 Q* = Q Excitation table State diagram
Clocked T Flip-flops Some versions of the T flip-flop operate under clock pulse control, as shown in Fig. 6.35a. In this case, the flip-flop toggles if T = 1 when the clock makes a high-to-low transition and holds its present state if T = 0 when the flip-flop is clocked. The operation of a clocked T flip-flop is described by the excitation table given in Fig The equivalent circuit of the clocked T flip-flop, shown in Fig. 6.35b, is simply a JK flip-flop with inputs J = K = T, and its C input driven by the clock signal. Another variation of the clocked T flip-flop is shown in Fig. 6.37a.
Clocked T Flip-Flop Figure 6.35 Logic symbolFunctional equivalent
Excitation Table for Clocked T Flip-Flops Figure 6.36 Q* = TQ + TQ
The Clocked T Flip-flop (a) logic symbol (b) Timing diagram Figure 6.37
Table 6.3 Summary of Latch and Flip-Flop Characteristics Device Characteristic Equation SR latch Q* = S + RQ Gated SR latch Q* = SC +QR + CQ D latch Q* = DC + CQ SR flip-flopQ* = S + RQ D flip-flopQ* = D JK flip-flopQ* = KQ + JQ T flip-flop (edge-triggered)Q* = Q T flip-flop (clocked) Q* = TQ + TQ