ReturnNext  Latch : a sequential device that watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal.

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ReturnNext  Latch : a sequential device that watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal. 7.2 Latches and Flip-Flops  Flip-flop: a sequential device that normally samples its inputs and changes its outputs only at times determined by a clocking signal.

 7.2.1 S-R Latch NextBackReturn 7.2 Latches and Flip-Flops Q R S Q Q n Q n 0 1 1 0 0* 0* 0 0 1 1 0 1 Q n+1 Q n+1 S R 2. Function table 1. Logic diagram Reset Set Next state Primary state Metastable

NextBackReturn 7.2 Latches and Flip-Flops 3. Functional behavior S R Q Q S R Q Q 4. Characteristic equation

NextBackReturn 7.2 Latches and Flip-Flops 5. Timing diagram  Propagation delay: t pLH(SQ), t pHL(RQ) S R Q t pLH(SQ) t pHL(RQ) t pw(min)  Minimum pulse width: t pw(min)

NextBackReturn 7.2 Latches and Flip-Flops  7.2.2 S-R Latch Q S R Q 1* 1* 1 0 0 1 Q n 0 0 0 1 1 0 1 1 Q n+1 S R

NextBackReturn 7.2 Latches and Flip-Flops  7.2.3 S-R Latch with Enable Q S C R Q  Functional behavior (See P538 Figure 7-11) S Q R Q S Q C R Q S Q R Q  Logic symbol

The D latch eliminates the SR=1 problem of the S-R latch, but dose not eliminate the metastability problem.(P539) NextBackReturn 7.2 Latches and Flip-Flops  7.2.4 D Latch Q D C Q 0 1 1 0 Q 1 0 1 0 x Q n+1 C D  Characteristic equation S-R latchs are useful in control application, a D (data) latch may be used to store bits of information.

NextBackReturn 7.2 Latches and Flip-Flops  7.2.5 Edge-Triggered D Latch  A positive-edge-triggered D flip-flop combines a pair of D latches, to create a circuit that samples its D input and changes its Q and QN outputs only at the rising edge of a controlling CLK signal. D Q C Q D Q C Q D CLK QM Q Q masterslave

NextBackReturn 7.2 Latches and Flip-Flops The master is open all the while that CLK is 0, The slave is open all the while that CLK is 1. D Q CLK QM 0 1 1 0 Q n 0 1 x 0 x 1 Q n+1 Q n+1 D CLK D Q CLK Q Positive- edge- triggered

NextBackReturn 7.2 Latches and Flip-Flops  Timing diagram CLK D Q t pLH(CQ) t pHL(CQ) t setup t hold <t setup

NextBackReturn 7.2 Latches and Flip-Flops  Negative-edge-triggered D flip-flop D Q C Q D Q C Q D CLK QM Q Q master slave  Asynchronous inputs (preset and clear inputs) D Q CLK Q PR CLR  Edge-triggered D flip- flop with enable D Q EN CLK Q Negative- edge- triggered D Q CLK Q

NextBackReturn 7.2 Latches and Flip-Flops  7.2.6 Master/Slave S-R Flip-Flop  Master/Slave S-R Flip-Flop output value depends on input values not just at the falling edge, but during the entire interval in which C is 1 prior to the falling edge. S Q C R Q S Q C R Q S C QM Q QN masterslave R

NextBackReturn 7.2 Latches and Flip-Flops S Q C R Q Q n 0 1 1 0 Undef. x x 0 0 0 1 1 0 1 Q n+1 S R C  7.2.7 Master/Slave J-K Flip-Flop (P546 Figure 7-26, Figure 7-27) Master/slave flip-flope

BackReturn 7.2 Latches and Flip-Flops  7.2.8 Edge-Triggered J-K Flip-Flop (P547~548 Figure 7-28, Figure 7-29)  7.2.9 T Flip-Flop (P549 Figure 7-31 ~7-33)

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