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1 Chapter 8 Flip-Flops and Related Devices

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2 Figure 8--1 Two versions of SET-RESET (S-R) latches S-R (Set-Reset) Latch

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3 Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b).

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4 Figure 8--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition.

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8 Figure 8--4 Logic symbols for the S-R and S-R latch.

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9 Figure 8-5 : Example 8-1

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10 Figure 8--6 The S-R latch used to eliminate switch contact bounce. Application Example

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11 Figure 8--7 The 74LS279 quad S-R latch.

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12 Figure 8--8 A gated S-R latch. Gated S-R Latch

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13 Figure 8--9 : Example 8-2

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14 Figure A gated D latch. Gated D Latch

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15 Figure 8—11 : Example 8-3

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16 Figure The 74LS75 quad gated D latches.

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17 Figure Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered). Edge-Triggered Flip-Flops

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18 Figure Operation of a positive edge-triggered S-R flip-flop.

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20 Figure : Example 8-4 Determine output waveform

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21 Figure 8--16

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22 Figure Edge triggering.

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23 Figure Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse.

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24 Figure Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.

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25 Figure A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.

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27 Figure : Example 8-5

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28 Figure A simplified logic diagram for a positive edge-triggered J-K flip-flop.

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29 Figure Transitions illustrating the toggle operation when J =1 and K = 1.

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31 Figure : Example 8-6

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32 Figure : Example 8-7

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33 Figure Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

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34 Figure Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.

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35 Figure Example 8-8

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36 Figure Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flops.

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37 Figure Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flops.

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38 Figure 8—31 : Example 8-9

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39 Figure Basic logic diagram for a master-slave J-K flip-flop. Master-Slave Flip-Flops

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41 Figure Pulse-triggered (master-slave) J-K flip-flop logic symbols.

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42 Figure : Example 8-10

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43 Figure Propagation delays, clock to output. Flip-Flop Operating Characteristics

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44 Figure Propagation delays, preset input to output and clear input to output.

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45 Figure Set-up time (t s ). The logic level must be present on the D input for a time equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry.

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46 Figure Hold time (t h ). The logic level must remain on the D input for a time equal to or greater than t h after the triggering edge of the clock pulse for reliable data entry.

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48 Figure Example of flip-flops used in a basic register for parallel data storage. Flip-Flop Application Parallel Data Storage

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49 Figure The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK. Application: Frequency Division

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50 Figure Example of two J-K flip-flops used to divide the clock frequency by 4. Q A is one-half and Q B is one-fourth the frequency of CLK.

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51 Figure : Example 8-11

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52 Figure 8--43

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53 Figure Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown. Application: Counting

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54 Figure : Example 8-12

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55 Figure 8--46

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