1. ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2. 2 2 CMOS Inverter Connect the following terminals of a PMOS and an NMOS –Gates –Drains V in V out V dd Gnd V out V in V in = HIGH V out = LOW (Gnd) ON OFF V dd Gnd V out V in V in = LOW V out = HIGH (V dd ) ON OFF V dd PMOS Ground NMOS

3. 3 3 CMOS Voltage Transfer Characteristics V dd Gnd V in V out PMOS NMOS OFF: V_GateToSource < V_Threshold LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource Note that in the CMOS Inverter  V_GateToSource = V_in

4. 4 4 Pull-Up and Pull-Down Network CMOS network consists of a Pull-UP Network (PUN) and a Pull-Down Network (PDN) PUN consists of a set of PMOS transistors PDN consists of a set of NMOS transistors PUN and PDN implementations are complimentary to each other –PMOS  NOMS –Series topology  Parallel topology …. I0I0 I1I1 I n-1 OUPTUT V dd PUN Gnd PDN

5. 5 5 PUN/PDN of a CMOS Inverter AB 01 1Z AB 0Z 10 AB 01 10 Pull-Up Network Pull-Down Network Combined CMOS Network V dd A Gnd B CMOS Inverter

6. 6 6 Gate Symbol of a CMOS Inverter V dd A Gnd B CMOS Inverter AB B = Ā

7. 7 7 PUN/PDN of a NAND Gate ABC 001 011 101 11Z ABC 00Z 01Z 10Z 110 Pull-Up Network Pull-Down Network V dd A B A B C

8. 8 8 PUN/PDN of a NAND Gate ABC 001 011 101 11Z ABC 00Z 01Z 10Z 110 ABC 001 011 101 110 Pull-Up Network Pull-Down Network Combined CMOS Network V dd A B A B C

9. 9 9 NAND Gate Symbol ABC 001 011 101 110 V dd A B A B C A B C Truth Table

10. 10 PUN/PDN of a NOR Gate ABC 001 01Z 10Z 11Z ABC 00Z 010 100 110 Pull-Up Network Pull-Down Network V dd A C B A B

11. 11 PUN/PDN of a NOR Gate ABC 001 01Z 10Z 11Z ABC 00Z 010 100 110 ABC 001 010 100 110 Pull-Up Network Pull-Down Network Combined CMOS Network A C B A B V dd

12. 12 NOR Gate Symbol ABC 001 010 100 110 A B C Truth Table A C B A B V dd

13. 13 How about an AND gate V dd A B A Gnd C NAND Inverter B C = A B A B C

14. 14 An OR Gate A B A B V dd Gnd C Inverter NOR A B C

15. 15 What’s the Function of the following CMOS Network? ABC 00Z 011 101 11Z ABC 000 01Z 10Z 110 ABC 000 011 101 110 Pull-Up Network Pull-Down Network Combined CMOS Network XOR Function = XOR V dd C

16. 16 Yet Another XOR CMOS Network V dd C ABC 00Z 011 101 11Z ABC 000 01Z 10Z 110 ABC 000 011 101 110 Pull-Up Network Pull-Down Network Combined CMOS Network XOR Function = XOR

17. 17 Exclusive-OR (XOR) Gate V dd C ABC 000 011 101 110 A B C Truth Table

18. 18 XNOR How about XNOR Gate ABC 001 010 100 111 A B C Truth Table How do we draw the corresponding CMOS network given a Boolean equation?

19. 19 XNOR How about XNOR Gate ABC 001 010 100 111 A B C Truth Table V dd C XOR Inverter

20. 20 A Systematic Method (I) Start from Pull-Up Network Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN PUNDraw PUN using PMOS based on the Boolean eqn –ANDseries –AND operation drawn in series –ORparallel –OR operation drawn in parallel variableInvert each variable of the Boolean eqn as the gate input for each PMOS in the PUN PDNDraw PDN using NMOS in complementary form –Parallel (PUN) to series (PDN) –Series (PUN) to parallel (PDN) Label with the same inputs of PUN Label the output

21. 21 A Systematic Method (II) Start from Pull-Down Network Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN Invert the Boolean eqn PDNWith the Right-Hand Side of the newly inverted equation, Draw PDN using NMOS –ANDseries –AND operation drawn in series –ORparallel –OR operation drawn in parallel variableLabel each variable of the Boolean eqn as the gate input for each NMOS in the PDN PUNDraw PUN using PMOS in complementary form –Parallel (PUN) to series (PDN) –Series (PUN) to parallel (PDN) Label with the same inputs of PUN Label the output

22. 22 Systematic Approaches Note that both methods lead to exactly the same implementation of a CMOS network The reason to invert Output equation in (II) is because –Output (F) is conducting to “ ground ”, i.e. 0, when there is a path formed by input NMOS transistors –Inversion will force the desired result from the equation Example –F=Ā · C + B: When (A=0 and C=1) or B=1, F=1. However, in the PDN (NMOS) of a CMOS network, F=0, i.e. an inverse result. –Revisit how a NAND CMOS network is implemented Inverting each PMOS input in (I) follow the same reasoning

23. 23 Example 1 (Method I) In series In parallel Vdd (1) Draw the Pull-Up Network

24. 24 Example 1 (Method I) In series In parallel Vdd (2) Assign the complemented input A C B

25. 25 Example 1 (Method I) In series In parallel Vdd (3) Draw the Pull-Down Network in the complementary form A C B A C

26. 26 Example 1 (Method I) In series In parallel Vdd (3) Draw the Pull-Down Network in the complementary form A C B A CB

27. 27 Example 1 (Method I) In series In parallel Vdd Label the output F A C B A CB F

28. 28 Example 1 (Method I) In series In parallel Vdd A C B A CB F ABCF 0000 0010 0101 0111 1001 1010 1101 1111 Truth Table

29. 29 Drawing the Schematic using Method II Vdd A C B A CB F This is exactly the same CMOS network with the schematic by Method I

30. 30 An Alternative for XNOR Gate (Method I) ABC 001 010 100 111 A B C Truth Table V dd C

31. 31 Example 3 Start from the innermost term A B D AC A D

32. 32 Example 3 Start from the innermost term A B D AC A D A C

33. 33 Example 3 Start from the innermost term A B D AC A D A C B

34. 34 Example 3 Start from the innermost term A B D AC A D A C B Vdd F Pull-Up Network Pull-Down Network

35. 35 Example 4 Start from the innermost term A B D A C A D A C B Vdd F E D E D Pull-Down Network Pull-Up Network

36. 36 Another Example How ??