Lecture 21 Today we will Revisit the CMOS inverter, concentrating on logic 0 and logic 1 inputs Come up with an easy model for MOS transistors involved.
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1 Lecture 21Today we willRevisit the CMOS inverter, concentrating on logic 0 and logic 1 inputsCome up with an easy model for MOS transistors involved in CMOS digital computationInvestigate the “complementary” nature of CMOS logic circuitsIntroduce CMOS NAND and NORDetermine the effective R and C for CMOS logic transitions
5 Model for Digital Computation This leads us to a simpler model for transistors in CMOS circuits, when VIN is fully logic 0 or logic 1.VGS = VDD (for NMOS)VGS = -VDD (for PMOS)VGS = 0 VDGSDGSTransistor is not cutoff, but zero current flow of partner transistor causes VDS = 0 V.Transistor is cutoff.Zero current flow.
6 Practice Use this model to find VOUT for the circuits below. VDD VDD VIN= 0 VVOUTVOUTVIN= VDD
8 More Practice Verify the logical operation of the CMOS NAND circuit: VDDVDDSSSSA= 0VA= 0VB= 0VB= VDDSSSS
9 More Practice Verify the logical operation of the CMOS NAND circuit: VDDVDDSSSSA= VDDA= VDDB= 0VB= VDDSSSS
10 CMOS NetworksNotice that VOUT gets connected to either VDD or ground by “active” (not cutoff) transistors.We say that these active transistors are “pulling up” or “pulling down” the output.NMOS transistors = pull-down networkPMOS transistors = pull-up networkThese networks had better be complementary or VOUT could be “floating”—or attached to both VDD and ground at the same time.
11 CMOS NAND vs. NORVDDABSVDDABSCMOS NORCMOS NANDABA+B
12 Complementary Networks If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS.The reverse is also true.Determining the logic function from CMOS circuit is not hard:Look at the NMOS half. It will tell you when the output is logic zero.Parallel transistors: “like or”Series transistors: “like and”
13 Resistance and Capacitance VGS > VTH(n)gate-+drainmetalmetaloxide insulatormetaln-type___eee_een-type+++_+++____p-typehhhhhhhhhhmetalThe separation of charge by the oxide insulator creates a natural capacitance in the transistor from gate to source.The silicon through which ID flows has a natural resistance.There are other sources of capacitance and resistance too.
14 Gate Delay—The Full Picture SVDDVOUT1DSVDDVOUT2eVINeSuppose VIN abruptly changed from logic 0 to logic 1.VOUT1 may not change quickly, since is attached to the gates of the next inverter.These gates must collect/discharge electrons to change voltage.Each gate attached to the output contributes a capacitance.
15 Gate Delay—The Full Picture SVDDVOUT1DSVDDVOUT2eVINeWhere will these electrons come from/go to?No charges can pass through the cutoff transistor.Charges will go through the pull-down/pull-up transistors to ground. These transistors contribute resistance.
16 Computing Gate Delay tp = (ln 2)RC SVDDVOUT1DSVDDVOUT2VINtp = (ln 2)RC1. Determine the capacitance of each gate attached to the output. These combine in parallel. Higher fan-out = more capacitance.2. Determine which transistors are pulling-up or pulling-down the output. Each contributes a resistance, and may need to be combined in series and/or parallel.3. The C from 1) and R from 2) are the RC for the VOUT1 transition.
17 Example Suppose we have the following circuit: If A and B both transition fromlogic 1 to logic 0 at t = 0,find the voltage at the NANDoutput, VOUT(t), for t ≥ 0.Logic 0 = 0 VLogic 1 = 1 VNMOS resistanceRn = 1 kWPMOS resistanceRp = 2 kWGate capacitanceCG = 50 pF
18 Answer VOUT(t) = 0 + (1-0) e-t/(2 kW 200 pF) V VOUT(t) = e-t/(400 ns) VA and B both transition from 0 to 1. Since VOUT comes out of a NAND of A with B, VOUT transitions from 1 to 0.VOUT(0) = 1 V VOUT,f = 0 VSince the output is transitioning from 1 to 0, it is being pulled down. Both NMOS transistors in the NAND were previously cutoff, but are now active. The NMOS in the NAND are in series, so the resistances add:R = 2 RN = 2 kWThe output in question feeds into 2 logic gate inputs (one inverter, one NOR). Each CMOS input is attached to two transistors. Thus we have 2 x 2 = 4 gate capacitances to charge. All capacitances are in parallel, so they add:C = 4 CG = 200 pF