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1 Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion. Digital CMOS Logic Circuits CMOS digital circuits: small size ease of fabrication low power dissipation CMOS Inverter

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2 Figure 10.6 Circuit for analyzing the propagation delay of the inverter formed by Q 1 and Q 2, which is driving an identical inverter formed by Q 3 and Q 4. Dynamic Operation of CMOS Inverter

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3 Figure 10.7 Equivalent circuits for determining the propagation delays (a) t PHL and (b) t PLH of the inverter.

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4 Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors. Basic Structure of CMOS Logic Gate Circuits alternative circuit symbols

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5 Figure 10.12 A two-input CMOS NOR gate. CMOS NOR Gate

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6 Figure 10.13 A two-input CMOS NAND gate. CMOS NAND Gate

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7 Figure 10.14 CMOS realization of a complex gate.

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8 Figure 10.15 Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10.25). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (10.26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10.27). CMOS XOR Gate

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9 Figure 10.16 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of Q N and Q P, respectively, of the basic inverter. Transistor Sizing

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10 Figure 10.17 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of Q N and Q P, respectively, of the basic inverter.

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