1. S. Reda VLSI Design Design and Implementation of VLSI Systems (EN1600) lecture09 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. S. Reda VLSI Design Summary of transistor operation NMOS transistor PMOS transistor

3. S. Reda VLSI Design DC transfer characteristics

4. S. Reda VLSI Design PMOS on (linear), NMOS off Vin = 0

5. S. Reda VLSI Design PMOS on (linear), NMOS on (saturation) V in = 0.2V DD

6. S. Reda VLSI Design PMOS on (linear ~ sat) and NMOS (sat) V in = 0.4V DD

7. S. Reda VLSI Design PMOS on (sat) NMOS on (linear) Vin = 0.6VDD

8. S. Reda VLSI Design PMOS on (off ~ linear) and NMOS on (linear) Vin = 0.8VDD

9. S. Reda VLSI Design NMOS on (linear) and PMOS cut off Vin = VDD

10. S. Reda VLSI Design Summary of voltage transfer function A B C E D

11. S. Reda VLSI Design Noise margins

12. S. Reda VLSI Design CMOS inverter noise margins desired regions of operation

13. S. Reda VLSI Design What is the impact of altering the PMOS width in comparison to the NMOS width on the DC char? V in3 I dsn, |I dsp | V out V DD V in3 V V If we increase (decrease) the width of PMOS compared to NMOS  for the same input voltage, a higher (lower) output voltage is obtained V in V out

14. S. Reda VLSI Design Impact of skewing transistor sizes on inverter noise margins  Increasing (decreasing) PMOS width to NMOS width increases (decreases) the low noise margin and decreases (increases) the high noise margin

15. S. Reda VLSI Design Pass transistor DC characteristics  As the source can rise to within a threshold voltage of the gate, the output of several transistors in series is no more degraded than that of a single transistor

16. S. Reda VLSI Design Summary Ideal transistor characteristics Non-ideal transistor characteristics Inverter DC transfer characteristics  Simulation with SPICE and integration with L-Edit