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**CT455: Computer Organization Logic gate**

CS1103 Digital Logic Design CT455: Computer Organization Logic gate

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**Lecture 4: Logic Gates and Circuits**

The Inverter The AND Gate The OR Gate The NAND Gate The NOR Gate The XOR Gate The XNOR Gate Drawing Logic Circuit Analysing Logic Circuit Propagation Delay

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**Lecture 4: Logic Gates and Circuits**

Universal Gates: NAND and NOR NAND Gate NOR Gate Implementation using NAND Gates Implementation using NOR Gates Implementation of SOP Expressions Implementation of POS Expressions Positive and Negative Logic Integrated Circuit Logic Families

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**Digital (logic) Elements: Gates**

Digital devices or gates have one or more inputs and produce an output that is a function of the current input value(s). All inputs and outputs are binary and can only take the values 0 or 1 A gate is called a combinational circuit because the output only depends on the current input combination. Digital circuits are created by using a number of connected gates such as the output of a gate is connected to to the input of one or more gates in such a way to achieve specific outputs for input values. Digital or logic design is concerned with the design of such circuits.

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**Chapter 1: Introduction**

Hardware consists of a few simple building blocks These are called logic gates AND, OR, NOT, … NAND, NOR, XOR, … Logic gates are built using transistors NOT gate can be implemented by a single transistor AND gate requires 3 transistors Transistors are the fundamental devices Pentium consists of 3 million transistors Compaq Alpha consists of 9 million transistors Now we can build chips with more than 100 million transistors CS1103 Chapter 1: Introduction

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**(ANSI/IEEE Standard 91-1984)**

Logic Gates Gate Symbols a b a.b a+b a' (a+b)' (a.b)' a b & 1 AND 1 =1 OR NOT NAND NOR Symbol set 1 Symbol set 2 (ANSI/IEEE Standard ) EXCLUSIVE OR

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Truth Tables Provides a listing of every possible combination of values of binary inputs to a digital circuit and the corresponding outputs. Example (2 inputs, 2 outputs): inputs Truth table outputs inputs outputs x y x . y x + y 1 x x . y Digital circuit y x + y

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**Chapter 1: Introduction**

Basic Concepts Simple gates AND OR NOT Functionality can be expressed by a truth table A truth table lists output for each possible input combination Other methods Logic expressions Logic diagrams CS1103 Chapter 1: Introduction

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**Basic Concepts (cont’d)**

Additional useful gates NAND NOR XOR NAND = AND + NOT NOR = OR + NOT XOR implements exclusive-OR function NAND and NOR gates require only 2 transistors AND and OR need 3 transistors! CS1103 Chapter 1: Introduction

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**Realizing Logic in Hardware**

Boolean Algebra and truth tables are essential important tools to express logical relationships. To use these tools in the real world , we must have some physical way to represent TRUE and FALSE (T and F). In, digital electronic circuits, T and F are represented by voltage levels: The transistor-transistor logic (TTL) 74LS family of digital integrated circuits produces two voltage levels: < .5V which represents low voltage L (0) and, > 2.7V which represents high voltage H (1) for the digital device.

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**Electronic Logic Gates**

Electrical Signals and Logic Values A signal that is set to logic 1 is said to be asserted, active, or true. An active-high signal is asserted when it is high (positive logic). An active-low signal is asserted when it is low (negative logic). CS1103 Chapter 1: Introduction

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**Logic Gates: The Inverter**

Application of the inverter: complement. 1 Binary number 1’s Complement

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**Logic Gates: The AND Gate**

B A.B &

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**Logic Gates: The AND Gate**

Application of the AND Gate 1 sec A Enable Counter Reset to zero between Enable pulses Register, decode and frequency display

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**Logic Gates: The OR Gate**

1 A B A+B

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**Logic Gates: The NAND Gate**

& A B (A.B)' NAND Negative-OR

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**Logic Gates: The NOR Gate**

1 A B (A+B)' NOR Negative-AND

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**Logic Gates: The XOR Gate**

=1 A B A B

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**Logic Gates: The XNOR Gate**

B (A B)' A B (A B)' =1

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**Basic Concepts (cont’d)**

Proving NAND gate is universal CS1103 Chapter 1: Introduction

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**Basic Concepts (cont’d)**

Proving NOR gate is universal CS1103 Chapter 1: Introduction

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Drawing Logic Circuit When a Boolean expression is provided, we can easily draw the logic circuit. Examples: (i) F1 = xyz' (note the use of a 3-input AND gate) x y z F1 z'

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Drawing Logic Circuit (ii) F2 = x + y'z (can assume that variables and their complements are available) x y' z F2 y'z (iii) F3 = xy' + x'z x' z F3 x'z xy' x y'

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**Analysing Logic Circuit**

When a logic circuit is provided, we can analyse the circuit to obtain the logic expression. Example: What is the Boolean expression of F4? A'B' A' B' C F4 A'B'+C (A'B'+C)' F4 = (A'B'+C)' = (A+B).C'

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**Logic Functions (cont’d)**

3-input majority function A B C F Logical expression form F = A B + B C + A C CS1103 Chapter 1: Introduction

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Propagation Delay Every logic gate experiences some delay (though very small) in propagating signals forward. This delay is called Gate (Propagation) Delay. Formally, it is the average transition time taken for the output signal of the gate to change in response to changes in the input signals. Three different propagation delay times associated with a logic gate: tPHL: output changing from the High level to Low level tPLH: output changing from the Low level to High level tPD=(tPLH + tPHL)/ (average propagation delay)

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Propagation Delay Input Output Output Input H L tPHL tPLH

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Propagation Delay A B C In reality, output signals normally lag behind input signals: 1 time Signal for C Signal for B Signal for A Ideally, no delay: 1 time Signal for C Signal for B Signal for A

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**Calculation of Circuit Delays**

Amount of propagation delay per gate depends on: (i) gate type (AND, OR, NOT, etc) (ii) transistor technology used (TTL,ECL,CMOS etc), (iii) miniaturisation (SSI, MSI, LSI, VLSI) To simplify matters, one can assume (i) an average delay time per gate, or (ii) an average delay time per gate-type. Propagation delay of logic circuit = longest time it takes for the input signal(s) to propagate to the output(s). = earliest time for output signal(s) to stabilise, given that input signals are stable at time 0.

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**Calculation of Circuit Delays**

In general, given a logic gate with delay, t. Logic Gate t1 t2 tn : max (t1, t2, ..., tn ) + t If inputs are stable at times t1,t2,..,tn, respectively; then the earliest time in which the output will be stable is: max(t1, t2, .., tn) + t To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.

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**Calculation of Circuit Delays**

As a simple example, consider the full adder circuit where all inputs are available at time 0. (Assume each gate has delay t.) X Y S C Z max(0,0)+t = t t max(t,0)+t = 2t max(t,2t)+t = 3t 2t where outputs S and C, experience delays of 2t and 3t, respectively.

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**Universal Gates: NAND and NOR**

AND/OR/NOT gates are sufficient for building any Boolean functions. We call the set {AND, OR, NOT} a complete set of logic. However, other gates are also used because: (i) usefulness (ii) economical on transistors (iii) self-sufficient NAND/NOR: economical, self-sufficient XOR: useful (e.g. parity bit generation)

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**(x.x)' = x' (T1: idempotency)**

NAND Gate NAND gate is self-sufficient (can build any logic circuit with it). Therefore, {NAND} is also a complete set of logic. Can be used to implement AND/OR/NOT. Implementing an inverter using NAND gate: x x' (x.x)' = x' (T1: idempotency)

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**NAND Gate Implementing AND using NAND gates:**

x x.y y (x.y)' ((xy)'(xy)')' = ((xy)')' idempotency = (xy) involution Implementing OR using NAND gates: x x+y y x' y' ((xx)'(yy)')' = (x'y')' idempotency = x''+y'' DeMorgan = x+y involution

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**(x+x)' = x' (T1: idempotency)**

NOR Gate NOR gate is also self-sufficient. Therefore, {NOR} is also a complete set of logic Can be used to implement AND/OR/NOT. Implementing an inverter using NOR gate: x x' (x+x)' = x' (T1: idempotency)

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**NOR Gate Implementing AND using NOR gates:**

x x.y y x' y' ((x+x)'+(y+y)')'=(x'+y')' idempotency = x''.y'' DeMorgan = x.y involution Implementing OR using NOR gates: x x+y y (x+y)' ((x+y)'+(x+y)')' = ((x+y)')' idempotency = (x+y) involution

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**Implementation using NAND gates**

Possible to implement any Boolean expression using NAND gates. Procedure: (i) Obtain sum-of-products Boolean expression: e.g. F3 = xy'+x'z (ii) Use DeMorgan theorem to obtain expression using 2-level NAND gates = (xy'+x'z)' ' involution = ((xy')' . (x'z)')' DeMorgan

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**Implementation using NAND gates**

x' z F3 (x'z)' (xy')' x y' F3 = ((xy')'.(x'z)') ' = xy' + x'z

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**Implementation using NOR gates**

Possible to implement any Boolean expression using NOR gates. Procedure: (i) Obtain product-of-sums Boolean expression: e.g. F6 = (x+y').(x'+z) (ii) Use DeMorgan theorem to obtain expression using 2-level NOR gates. = ((x+y').(x'+z))' ' involution = ((x+y')'+(x'+z)')' DeMorgan

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**Implementation using NOR gates**

x' z F6 (x'+z)' (x+y')' x y' F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)

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**Chapter 1: Introduction**

Logical Equivalence All three circuits implement F = A B function CS1103 Chapter 1: Introduction

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**Logical Equivalence (cont’d)**

Derivation of logical expression from a circuit Trace from the input to output Write down intermediate logical expressions along the path CS1103 Chapter 1: Introduction

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**Logical Equivalence (cont’d)**

Proving logical equivalence: Truth table method A B F1 = A B F3 = (A + B) (A + B) (A + B) CS1103 Chapter 1: Introduction

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**Implementation of SOP Expressions**

Sum-of-Products expressions can be implemented using: 2-level AND-OR logic circuits 2-level NAND logic circuits AND-OR logic circuit F A B D C E F = AB + CD + E

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**Implementation of SOP Expressions**

NAND-NAND circuit (by circuit transformation) a) add double bubbles b) change OR-with- inverted-inputs to NAND & bubbles at inputs to their complements F A B D C E E'

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**Deriving Logical Expressions (cont’d)**

3-input majority function A B C F SOP logical expression Four product terms Because there are 4 rows with a 1 output F = A B C + A B C +A B C + A B C Sigma notation S(3, 5, 6, 7) CS1103 Chapter 1: Introduction

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**Brute Force Method of Implementation**

3-input even-parity function A B C F SOP implementation CS1103 Chapter 1: Introduction

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**Implementation of POS Expressions**

Product-of-Sums expressions can be implemented using: 2-level OR-AND logic circuits 2-level NOR logic circuits OR-AND logic circuit G A B D C E G = (A+B).(C+D).E

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**Implementation of POS Expressions**

NOR-NOR circuit (by circuit transformation): a) add double bubbles b) changed AND-with- inverted-inputs to NOR & bubbles at inputs to their complements G A B D C E E'

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**Deriving Logical Expressions (cont’d)**

3-input majority function A B C F POS logical expression Four sum terms Because there are 4 rows with a 0 output F = (A + B + C) (A + B + C) (A + B + C) (A + B + C) Pi notation (0, 1, 2, 4 ) CS1103 Chapter 1: Introduction

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**Brute Force Method of Implementation**

3-input even-parity function A B C F POS implementation CS1103 Chapter 1: Introduction

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**Positive & Negative Logic**

In logic gates, usually: H (high voltage, 5V) = 1 L (low voltage, 0V) = 0 This convention – positive logic. However, the reverse convention, negative logic possible: H (high voltage) = 0 L (low voltage) = 1 Depending on convention, same gate may denote different Boolean function.

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**Positive & Negative Logic**

A signal that is set to logic 1 is said to be asserted, or active, or true. A signal that is set to logic 0 is said to be deasserted, or negated, or false. Active-high signal names are usually written in uncomplemented form. Active-low signal names are usually written in complemented form.

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**Positive & Negative Logic**

Positive logic: Enable Active High: 0: Disabled 1: Enabled Negative logic: Enable Active Low: 0: Enabled 1: Disabled

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**Integrated Circuit Logic Families**

Some digital integrated circuit families: TTL, CMOS, ECL. TTL: Transistor-Transistor Logic. Uses bipolar junction transistors Consists of a series of logic circuits: standard TTL, low-power TTL, Schottky TTL, low-power Schottky TTL, advanced Schottky TTL, etc.

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**Integrated Circuit Logic Families**

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**Integrated Circuit Logic Families**

CMOS: Complementary Metal-Oxide Semiconductor. Uses field-effect transistors ECL: Emitter Coupled Logic. Uses bipolar circuit technology. Has fastest switching speed but high power consumption.

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**Integrated Circuit Logic Families**

Performance characteristics Propagation delay time. Power dissipation. Fan-out: Fan-out of a gate is the maximum number of inputs that the gate can drive. Speed-power product (SPP): product of the propagation delay time and the power dissipation.

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**Drawing Logic Circuits**

When a Boolean expression is provided, we can easily draw the logic circuit. Examples: F1 = xyz' (note the use of a 3-input AND gate) x y z F1 z'

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**Analysing Logic Circuits**

When a logic circuit is provided, we can analyse the circuit to obtain the logic expression. Example: What is the Boolean expression of F4? A' B' C F4 A'B' A'B'+C (A'B'+C)' F4 = (A'B'+C)'

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**Analysing Logic Circuit**

Example: What is Boolean expression of F5? z F5 x y F5 =

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**Simple Circuit Design: Two-input Multiplexer**

Multiplexer with two input bits, A, B and a control input bit S and output Z. Depending on the value of S, the circuit is to transfer either the the value of A or B to the output Z A Truth table from circuit description Z B S A B Z Using logic design methods (to be studied later) we get the optimal logic function for Z Z = S’. A + S . B S S’. A A S Z S’. A + S . B B S . B

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**Analysis of Combinational Circuits (1)**

Digital Circuit Design: Word description of a function a set of switching equations hardware realization (gates, programmable logic devices, etc.) Digital Circuit Analysis: Hardware realization switching expressions, truth tables, timing diagrams, etc. Analysis is used To determine the behavior of the circuit To verify the correctness of the circuit To assist in converting the circuit to a different form. CS1103 Chapter 1: Introduction

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**Analysis of Combinational Circuits (2)**

Algebraic Method: Use switching algebra to derive a desired form. Example 2.33: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.21a). CS1103 Chapter 1: Introduction

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**Analysis of Combinational Circuits (3)**

Write switching expression for each gate output: The output is: Simplify the output function using switching algebra: [Eq. 2.24] [T8] [T5(b)] [T4(a)] = b c [Eq. 2.32] Therefore, f (a,b,c) = (b c)' = CS1103 Chapter 1: Introduction

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**Analysis of Combinational Circuits (4)**

Example 2.34: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.22). CS1103 Chapter 1: Introduction

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**Analysis of Combinational Circuits (5)**

Derive the output expression: f(a,b,c) = = [T8(b)] = [T8(a)] = [Eq. 2.24] = [P5(b)] = [P6(b), T4(a)] = [T4(a)] = [T9(a)] = [T7(a)] CS1103 Chapter 1: Introduction

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**Analysis of Combinational Circuits (6)**

Truth Table Method: Derive the truth table one gate at a time. The truth table for Example 2.34: CS1103 Chapter 1: Introduction

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**Analysis of Combinational Circuits (7)**

Analysis of Timing Diagrams Timing diagram is a graphical representation of input and output signal relationships over the time dimension. Timing diagrams may show intermediate signals and propagation delays. CS1103 Chapter 1: Introduction

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**Analysis of Combinational Circuits (8)**

Example 2.35: Derivation of truth table from a timing diagram CS1103 Chapter 1: Introduction

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**Chapter 1: Introduction**

CS1103 Chapter 1: Introduction

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Integrated Circuits An Integrated circuit (IC) is a number of logic gated fabricated on a single silicon chip. ICs can be classified according to how many gates they contain as follows: Small-Scale Integration (SSI): Contain 1 to 20 gates. Medium-Scale Integration (MSI): Contain 20 to 200 gates. Examples: Registers, decoders, counters. Large-Scale Integration (LSI): Contain 200 to 200,000 gates. Include small memories, some microprocessors, programmable logic devices. Very Large-Scale Integration (VLSI): Usually stated in terms of number of transistors contained usually over 1,000,000. Includes most microprocessors and memories.

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**Computer Hardware Generations**

The First Generation, : Vacuum Tubes, Relays, Mercury Delay Lines: ENIAC (Electronic Numerical Integrator and Computer): First electronic computer, vacuum tubes, 1500 relays, 5000 additions/sec. First stored program computer: EDSAC (Electronic Delay Storage Automatic Calculator). The Second Generation, : Discrete Transistors. (e.g IBM 7000 series, DEC PDP-1) The Third Generation, : Small and Medium-Scale Integrated (SSI, MSI) Circuits. (e.g. IBM 360 mainframe) The Fourth Generation, 1975-Present: The Microcomputer. VLSI-based Microprocessors.

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**Hierarchy of Computer Architecture**

High-Level Language Programs Assembly Language Programs Software I/O system Instr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware Datapath & Control Layout Machine Language Program Software/Hardware Boundary Hardware Microprogram Register Transfer Notation (RTN) Logic Diagrams Circuit Diagrams

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**Summary Logic Gates Drawing Logic Circuit Analysing Logic Circuit**

AND, OR, NOT NAND NOR Drawing Logic Circuit Analysing Logic Circuit Given a Boolean expression, draw the circuit. Given a circuit, find the function. Implementation of a Boolean expression using these Universal gates. Implementation of SOP and POS Expressions Positive and Negative Logic Concept of Minterm and Maxterm

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COMPUTER ARCHITECTURE TRUTH TABLES AND LOGIC GATES.

COMPUTER ARCHITECTURE TRUTH TABLES AND LOGIC GATES.

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