Presentation is loading. Please wait.

Presentation is loading. Please wait.

CT455: Computer Organization Logic gate. Lecture 4: Logic Gates and Circuits Logic Gates Logic Gates Logic Gates Logic Gates The Inverter The Inverter.

Similar presentations


Presentation on theme: "CT455: Computer Organization Logic gate. Lecture 4: Logic Gates and Circuits Logic Gates Logic Gates Logic Gates Logic Gates The Inverter The Inverter."— Presentation transcript:

1 CT455: Computer Organization Logic gate

2 Lecture 4: Logic Gates and Circuits Logic Gates Logic Gates Logic Gates Logic Gates The Inverter The Inverter The Inverter The Inverter The AND Gate The AND Gate The AND Gate The AND Gate The OR Gate The OR Gate The OR Gate The OR Gate The NAND Gate The NAND Gate The NAND Gate The NAND Gate The NOR Gate The NOR Gate The NOR Gate The NOR Gate The XOR Gate The XOR Gate The XOR Gate The XOR Gate The XNOR Gate The XNOR Gate The XNOR Gate The XNOR Gate Drawing Logic Circuit Drawing Logic Circuit Drawing Logic Circuit Drawing Logic Circuit Analysing Logic Circuit Analysing Logic Circuit Analysing Logic Circuit Analysing Logic Circuit Propagation Delay Propagation Delay Propagation Delay Propagation Delay

3 Lecture 4: Logic Gates and Circuits Universal Gates: NAND and NOR Universal Gates: NAND and NOR Universal Gates: NAND and NOR Universal Gates: NAND and NOR NAND Gate NAND Gate NAND Gate NAND Gate NOR Gate NOR Gate NOR Gate NOR Gate Implementation using NAND Gates Implementation using NAND Gates Implementation using NAND Gates Implementation using NAND Gates Implementation using NOR Gates Implementation using NOR Gates Implementation using NOR Gates Implementation using NOR Gates Implementation of SOP Expressions Implementation of SOP Expressions Implementation of SOP Expressions Implementation of SOP Expressions Implementation of POS Expressions Implementation of POS Expressions Implementation of POS Expressions Implementation of POS Expressions Positive and Negative Logic Positive and Negative Logic Positive and Negative Logic Positive and Negative Logic Integrated Circuit Logic Families Integrated Circuit Logic Families Integrated Circuit Logic Families Integrated Circuit Logic Families

4 Digital (logic) Elements: Gates Digital devices or gates have one or more inputs and produce an output that is a function of the current input value(s). All inputs and outputs are binary and can only take the values 0 or 1 A gate is called a combinational circuit because the output only depends on the current input combination. Digital circuits are created by using a number of connected gates such as the output of a gate is connected to to the input of one or more gates in such a way to achieve specific outputs for input values. Digital or logic design is concerned with the design of such circuits.

5 CS1103Chapter 1: Introduction Introduction Hardware consists of a few simple building blocks These are called logic gates These are called logic gates AND, OR, NOT, … NAND, NOR, XOR, … Logic gates are built using transistors NOT gate can be implemented by a single transistor AND gate requires 3 transistors Transistors are the fundamental devices Pentium consists of 3 million transistors Compaq Alpha consists of 9 million transistors Now we can build chips with more than 100 million transistors

6 Logic Gates Gate Symbols Gate Symbols EXCLUSIVE OR abab a.b abab a+b aa' abab (a+b)' abab (a.b)' abab a b abab a.b & abab a+b 1 AND aa' 1 abab (a.b)' & abab (a+b)' 1 abab a b =1 OR NOT NAND NOR Symbol set 1 Symbol set 2 (ANSI/IEEE Standard )

7 Truth Tables Provides a listing of every possible combination of values of binary inputs to a digital circuit and the corresponding outputs. Example (2 inputs, 2 outputs): Digital circuit inputs outputs x y inputs outputs x + y x. y Truth table

8 CS1103Chapter 1: Introduction Basic Concepts Simple gates AND AND OR OR NOT NOT Functionality can be expressed by a truth table A truth table lists output for each possible input combination A truth table lists output for each possible input combination Other methods Logic expressions Logic expressions Logic diagrams Logic diagrams

9 CS1103Chapter 1: Introduction Basic Concepts (contd) Additional useful gates NAND NAND NOR NOR XOR XOR NAND = AND + NOT NOR = OR + NOT XOR implements exclusive-OR function NAND and NOR gates require only 2 transistors AND and OR need 3 transistors! AND and OR need 3 transistors!

10 Realizing Logic in Hardware Boolean Algebra and truth tables are essential important tools to express logical relationships. To use these tools in the real world, we must have some physical way to represent TRUE and FALSE (T and F). In, digital electronic circuits, T and F are represented by voltage levels : The transistor-transistor logic (TTL) 74LS family of digital integrated circuits produces two voltage levels: The transistor-transistor logic (TTL) 74LS family of digital integrated circuits produces two voltage levels: <.5V which represents low voltage L (0) and, <.5V which represents low voltage L (0) and, > 2.7V which represents high voltage H (1) for the digital device.

11 CS1103Chapter 1: Introduction Electronic Logic Gates Electrical Signals and Logic Values A signal that is set to logic 1 is said to be asserted, active, or true. A signal that is set to logic 1 is said to be asserted, active, or true. An active-high signal is asserted when it is high (positive logic). An active-high signal is asserted when it is high (positive logic). An active-low signal is asserted when it is low (negative logic). An active-low signal is asserted when it is low (negative logic).

12 Logic Gates: The Inverter The Inverter The Inverter AA' A Application of the inverter: complement. Application of the inverter: complement Binary number 1s Complement

13 Logic Gates: The AND Gate The AND Gate The AND Gate ABAB A.B & ABAB

14 Logic Gates: The AND Gate Application of the AND Gate Application of the AND Gate 1 sec A Enable A Counter Reset to zero between Enable pulses Register, decode and frequency display

15 Logic Gates: The OR Gate The OR Gate The OR Gate 1 ABAB A+B ABAB

16 Logic Gates: The NAND Gate The NAND Gate The NAND Gate & ABAB (A.B)' ABAB ABAB NAND Negative-OR

17 Logic Gates: The NOR Gate The NOR Gate The NOR Gate NOR Negative-AND 1 ABAB (A+B)' ABAB (A+B)' ABAB

18 Logic Gates: The XOR Gate The XOR Gate The XOR Gate =1 ABAB A B ABAB

19 Logic Gates: The XNOR Gate The XNOR Gate The XNOR Gate ABAB (A B)' =1 ABAB (A B)'

20 CS1103Chapter 1: Introduction Basic Concepts (contd) Proving NAND gate is universal

21 CS1103Chapter 1: Introduction Basic Concepts (contd) Proving NOR gate is universal

22 Drawing Logic Circuit When a Boolean expression is provided, we can easily draw the logic circuit. When a Boolean expression is provided, we can easily draw the logic circuit. Examples: Examples: (i) F1 = xyz' (note the use of a 3-input AND gate) (i) F1 = xyz' (note the use of a 3-input AND gate) x y z F1 z'

23 Drawing Logic Circuit (ii) F2 = x + y'z (can assume that variables and their complements are available) (iii) F3 = xy' + x'z x y' z F2 y'z x' z F3 x'z xy' x y'

24 Analysing Logic Circuit When a logic circuit is provided, we can analyse the circuit to obtain the logic expression. When a logic circuit is provided, we can analyse the circuit to obtain the logic expression. Example: What is the Boolean expression of F4? Example: What is the Boolean expression of F4? A'B' A'B'+C(A'B'+C)' A' B' C F4 F4 = (A'B'+C)' = (A+B).C'

25 CS1103Chapter 1: Introduction Logic Functions (contd) 3-input majority function ABCF Logical expression form F = A B + B C + A C

26 Propagation Delay Every logic gate experiences some delay (though very small) in propagating signals forward. Every logic gate experiences some delay (though very small) in propagating signals forward. This delay is called Gate (Propagation) Delay. This delay is called Gate (Propagation) Delay. Formally, it is the average transition time taken for the output signal of the gate to change in response to changes in the input signals. Formally, it is the average transition time taken for the output signal of the gate to change in response to changes in the input signals. Three different propagation delay times associated with a logic gate: Three different propagation delay times associated with a logic gate: t PHL : output changing from the High level to Low level t PHL : output changing from the High level to Low level t PLH : output changing from the Low level to High level t PLH : output changing from the Low level to High level t PD =(t PLH + t PHL )/2 (average propagation delay) t PD =(t PLH + t PHL )/2 (average propagation delay)

27 Propagation Delay InputOutput Input H L L H t PHL t PLH

28 Propagation Delay ABC Ideally, no delay: Ideally, no delay: time Signal for C Signal for B Signal for A In reality, output signals normally lag behind input signals: In reality, output signals normally lag behind input signals: time Signal for C Signal for B Signal for A

29 Calculation of Circuit Delays Amount of propagation delay per gate depends on: Amount of propagation delay per gate depends on: (i) gate type (AND, OR, NOT, etc) (i) gate type (AND, OR, NOT, etc) (ii) transistor technology used (TTL,ECL,CMOS etc), (ii) transistor technology used (TTL,ECL,CMOS etc), (iii) miniaturisation (SSI, MSI, LSI, VLSI) (iii) miniaturisation (SSI, MSI, LSI, VLSI) To simplify matters, one can assume To simplify matters, one can assume (i) an average delay time per gate, or (i) an average delay time per gate, or (ii) an average delay time per gate-type. (ii) an average delay time per gate-type. Propagation delay of logic circuit Propagation delay of logic circuit = longest time it takes for the input signal(s) to propagate to the output(s). = earliest time for output signal(s) to stabilise, given that input signals are stable at time 0.

30 Calculation of Circuit Delays In general, given a logic gate with delay, t. In general, given a logic gate with delay, t. If inputs are stable at times t 1,t 2,..,t n, respectively; then the earliest time in which the output will be stable is: max(t 1, t 2,.., t n ) + t Logic Gate t1t1 t2t2 tntn :: max (t 1, t 2,..., t n ) + t To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates. To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.

31 Calculation of Circuit Delays As a simple example, consider the full adder circuit where all inputs are available at time 0. (Assume each gate has delay t.) As a simple example, consider the full adder circuit where all inputs are available at time 0. (Assume each gate has delay t.) where outputs S and C, experience delays of 2t and 3t, respectively. XYXY S C Z max(0,0)+t = t t max(t,0)+t = 2t max(t,2t)+t = 3t 2t

32 Universal Gates: NAND and NOR AND/OR/NOT gates are sufficient for building any Boolean functions. AND/OR/NOT gates are sufficient for building any Boolean functions. We call the set {AND, OR, NOT} a complete set of logic. We call the set {AND, OR, NOT} a complete set of logic. However, other gates are also used because: However, other gates are also used because: (i) usefulness (ii) economical on transistors (iii) self-sufficient NAND/NOR: economical, self-sufficient XOR: useful (e.g. parity bit generation)

33 NAND Gate NAND gate is self-sufficient (can build any logic circuit with it). NAND gate is self-sufficient (can build any logic circuit with it). Therefore, {NAND} is also a complete set of logic. Therefore, {NAND} is also a complete set of logic. Can be used to implement AND/OR/NOT. Can be used to implement AND/OR/NOT. Implementing an inverter using NAND gate: Implementing an inverter using NAND gate: (x.x)' = x' (T1: idempotency) xx'

34 NAND Gate ((xy)'(xy)')' = ((xy)')' idempotency = (xy) involution ((xx)'(yy)')' = (x'y')' idempotency = x''+y'' DeMorgan = x+y involution Implementing AND using NAND gates: Implementing AND using NAND gates: Implementing OR using NAND gates: Implementing OR using NAND gates: x x.y y (x.y)' x x+y y x' y'

35 NOR Gate NOR gate is also self-sufficient. NOR gate is also self-sufficient. Therefore, {NOR} is also a complete set of logic Therefore, {NOR} is also a complete set of logic Can be used to implement AND/OR/NOT. Can be used to implement AND/OR/NOT. Implementing an inverter using NOR gate: Implementing an inverter using NOR gate: (x+x)' = x' (T1: idempotency) xx'

36 NOR Gate ((x+x)'+(y+y)')'=(x'+y')' idempotency = x''.y'' DeMorgan = x.y involution ((x+y)'+(x+y)')' = ((x+y)')' idempotency = (x+y) involution Implementing AND using NOR gates: Implementing AND using NOR gates: Implementing OR using NOR gates: Implementing OR using NOR gates: x x+y y (x+y)' x x.y y x' y'

37 Implementation using NAND gates Possible to implement any Boolean expression using NAND gates. Possible to implement any Boolean expression using NAND gates.Procedure: (i) Obtain sum-of-products Boolean expression: e.g. F3 = xy'+x'z e.g. F3 = xy'+x'z (ii) Use DeMorgan theorem to obtain expression using 2-level NAND gates e.g. F3 = xy'+x'z e.g. F3 = xy'+x'z = (xy'+x'z)' ' involution = (xy'+x'z)' ' involution = ((xy')'. (x'z)')' DeMorgan = ((xy')'. (x'z)')' DeMorgan

38 Implementation using NAND gates F3 = ((xy')'.(x'z)') ' = xy' + x'z x' z F3 (x'z)' (xy')' x y'

39 Implementation using NOR gates Possible to implement any Boolean expression using NOR gates. Possible to implement any Boolean expression using NOR gates.Procedure: (i) Obtain product-of-sums Boolean expression: e.g. F6 = (x+y').(x'+z) e.g. F6 = (x+y').(x'+z) (ii) Use DeMorgan theorem to obtain expression using 2-level NOR gates. e.g. F6 = (x+y').(x'+z) e.g. F6 = (x+y').(x'+z) = ((x+y').(x'+z))' ' involution = ((x+y').(x'+z))' ' involution = ((x+y')'+(x'+z)')' DeMorgan = ((x+y')'+(x'+z)')' DeMorgan

40 Implementation using NOR gates F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z) x' z F6 (x'+z)' (x+y')' x y'

41 CS1103Chapter 1: Introduction Logical Equivalence All three circuits implement F = A B function

42 CS1103Chapter 1: Introduction Logical Equivalence (contd) Derivation of logical expression from a circuit Trace from the input to output Trace from the input to output Write down intermediate logical expressions along the path

43 CS1103Chapter 1: Introduction Logical Equivalence (contd) Proving logical equivalence: Truth table method A BF1 = A BF3 = (A + B) (A + B) (A + B)

44 Implementation of SOP Expressions Sum-of-Products expressions can be implemented using: Sum-of-Products expressions can be implemented using: 2-level AND-OR logic circuits 2-level AND-OR logic circuits 2-level NAND logic circuits 2-level NAND logic circuits AND-OR logic circuit AND-OR logic circuit F = AB + CD + E F A B D C E

45 Implementation of SOP Expressions NAND-NAND circuit (by circuit transformation) NAND-NAND circuit (by circuit transformation) a) add double bubbles a) add double bubbles b) change OR-with- b) change OR-with- inverted-inputs to NAND inverted-inputs to NAND & bubbles at inputs to & bubbles at inputs to their complements their complements F A B D C E A B D C E' F

46 CS1103Chapter 1: Introduction Deriving Logical Expressions (contd) 3-input majority function ABCF SOP logical expression Four product terms Because there are 4 rows with a 1 output Because there are 4 rows with a 1 output F = A B C + A B C +A B C + A B C Sigma notation S(3, 5, 6, 7)

47 CS1103Chapter 1: Introduction Brute Force Method of Implementation 3-input even-parity function ABCF SOP implementation

48 Implementation of POS Expressions Product-of-Sums expressions can be implemented using: Product-of-Sums expressions can be implemented using: 2-level OR-AND logic circuits 2-level OR-AND logic circuits 2-level NOR logic circuits 2-level NOR logic circuits OR-AND logic circuit OR-AND logic circuit G = (A+B).(C+D).E G A B D C E

49 Implementation of POS Expressions NOR-NOR circuit (by circuit transformation): NOR-NOR circuit (by circuit transformation): a) add double bubbles a) add double bubbles b) changed AND-with- b) changed AND-with- inverted-inputs to NOR inverted-inputs to NOR & bubbles at inputs to & bubbles at inputs to their complements their complements G A B D C E A B D C E' G

50 CS1103Chapter 1: Introduction Deriving Logical Expressions (contd) 3-input majority function ABCF POS logical expression Four sum terms Because there are 4 rows with a 0 output Because there are 4 rows with a 0 output F = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) Pi notation (0, 1, 2, 4 ) (0, 1, 2, 4 )

51 CS1103Chapter 1: Introduction Brute Force Method of Implementation 3-input even-parity function ABCF POS implementation

52 Positive & Negative Logic In logic gates, usually: In logic gates, usually: H (high voltage, 5V) = 1 H (high voltage, 5V) = 1 L (low voltage, 0V) = 0 L (low voltage, 0V) = 0 This convention – positive logic. This convention – positive logic. However, the reverse convention, negative logic possible: However, the reverse convention, negative logic possible: H (high voltage) = 0 H (high voltage) = 0 L (low voltage) = 1 L (low voltage) = 1 Depending on convention, same gate may denote different Boolean function. Depending on convention, same gate may denote different Boolean function.

53 Positive & Negative Logic A signal that is set to logic 1 is said to be asserted, or active, or true. A signal that is set to logic 1 is said to be asserted, or active, or true. A signal that is set to logic 0 is said to be deasserted, or negated, or false. A signal that is set to logic 0 is said to be deasserted, or negated, or false. Active-high signal names are usually written in uncomplemented form. Active-high signal names are usually written in uncomplemented form. Active-low signal names are usually written in complemented form. Active-low signal names are usually written in complemented form.

54 Positive & Negative Logic Positive logic: Negative logic: Enable Active High: 0: Disabled 1: Enabled Enable Active Low: 0: Enabled 1: Disabled

55 Integrated Circuit Logic Families Some digital integrated circuit families: TTL, CMOS, ECL. Some digital integrated circuit families: TTL, CMOS, ECL. TTL: Transistor-Transistor Logic. TTL: Transistor-Transistor Logic. Uses bipolar junction transistors Uses bipolar junction transistors Consists of a series of logic circuits: standard TTL, low- power TTL, Schottky TTL, low-power Schottky TTL, advanced Schottky TTL, etc. Consists of a series of logic circuits: standard TTL, low- power TTL, Schottky TTL, low-power Schottky TTL, advanced Schottky TTL, etc.

56 Integrated Circuit Logic Families

57 CMOS: Complementary Metal-Oxide Semiconductor. CMOS: Complementary Metal-Oxide Semiconductor. Uses field-effect transistors Uses field-effect transistors ECL: Emitter Coupled Logic. ECL: Emitter Coupled Logic. Uses bipolar circuit technology. Uses bipolar circuit technology. Has fastest switching speed but high power consumption. Has fastest switching speed but high power consumption.

58 Integrated Circuit Logic Families Performance characteristics Performance characteristics Propagation delay time. Propagation delay time. Power dissipation. Power dissipation. Fan-out: Fan-out of a gate is the maximum number of inputs that the gate can drive. Fan-out: Fan-out of a gate is the maximum number of inputs that the gate can drive. Speed-power product (SPP): product of the propagation delay time and the power dissipation. Speed-power product (SPP): product of the propagation delay time and the power dissipation.

59 Drawing Logic Circuits When a Boolean expression is provided, we can easily draw the logic circuit. Examples: F1 = xyz' F1 = xyz' (note the use of a 3-input AND gate) (note the use of a 3-input AND gate) x y z F1 z'

60 Analysing Logic Circuits When a logic circuit is provided, we can analyse the circuit to obtain the logic expression. Example: What is the Boolean expression of F4? A'B' A'B'+C (A'B'+C)' A' B' C F4 F4 = (A'B'+C)'

61 Analysing Logic Circuit Example: What is Boolean expression of F5? z F5 x y F5 =

62 Simple Circuit Design: Two-input Multiplexer Multiplexer with two input bits, A, B and a control input bit S and output Z. Depending on the value of S, the circuit is to transfer either the the value of A or B to the output Z A B Z S S A B Z Truth table from circuit description Using logic design methods (to be studied later) we get the optimal logic function for Z Z = S. A + S. B B Z A S S. A S. B S. A + S. B

63 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (1) Digital Circuit Design: Word description of a function Word description of a function a set of switching equations a set of switching equations hardware realization (gates, programmable logic devices, etc.) hardware realization (gates, programmable logic devices, etc.) Digital Circuit Analysis: Hardware realization Hardware realization switching expressions, truth tables, timing diagrams, etc. switching expressions, truth tables, timing diagrams, etc. Analysis is used To determine the behavior of the circuit To determine the behavior of the circuit To verify the correctness of the circuit To verify the correctness of the circuit To assist in converting the circuit to a different form. To assist in converting the circuit to a different form.

64 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (2) Algebraic Method: Use switching algebra to derive a desired form. Example 2.33: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.21a).

65 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (3) Write switching expression for each gate output: The output is: Simplify the output function using switching algebra: [Eq. 2.24] [Eq. 2.24][T8][T5(b)] [T4(a)] = b c[Eq. 2.32] Therefore, f (a,b,c) = (b c)' = Therefore, f (a,b,c) = (b c)' =

66 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (4) Example 2.34: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.22).

67 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (5) Derive the output expression: f(a,b,c) = =[T8(b)] =[T8(a)] =[Eq. 2.24] =[P5(b)] = [P6(b), T4(a)] =[T4(a)] =[T9(a)] =[T7(a)] =[Eq. 2.24]

68 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (6) Truth Table Method: Derive the truth table one gate at a time. The truth table for Example 2.34:

69 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (7) Analysis of Timing Diagrams Timing diagram is a graphical representation of input and output signal relationships over the time dimension. Timing diagram is a graphical representation of input and output signal relationships over the time dimension. Timing diagrams may show intermediate signals and propagation delays. Timing diagrams may show intermediate signals and propagation delays.

70 CS1103Chapter 1: Introduction Analysis of Combinational Circuits (8) Example 2.35: Derivation of truth table from a timing diagram

71 CS1103Chapter 1: Introduction

72 Integrated Circuits An Integrated circuit (IC) is a number of logic gated fabricated on a single silicon chip. ICs can be classified according to how many gates they contain as follows: Small-Scale Integration (SSI): Contain 1 to 20 gates. Small-Scale Integration (SSI): Contain 1 to 20 gates. Medium-Scale Integration (MSI): Contain 20 to 200 gates. Examples: Registers, decoders, counters. Medium-Scale Integration (MSI): Contain 20 to 200 gates. Examples: Registers, decoders, counters. Large-Scale Integration (LSI): Contain 200 to 200,000 gates. Include small memories, some microprocessors, programmable logic devices. Large-Scale Integration (LSI): Contain 200 to 200,000 gates. Include small memories, some microprocessors, programmable logic devices. Very Large-Scale Integration (VLSI): Usually stated in terms of number of transistors contained usually over 1,000,000. Includes most microprocessors and memories. Very Large-Scale Integration (VLSI): Usually stated in terms of number of transistors contained usually over 1,000,000. Includes most microprocessors and memories.

73 Computer Hardware Generations The First Generation, : Vacuum Tubes, Relays, Mercury Delay Lines: ENIAC (Electronic Numerical Integrator and Computer): First electronic computer, vacuum tubes, 1500 relays, 5000 additions/sec. ENIAC (Electronic Numerical Integrator and Computer): First electronic computer, vacuum tubes, 1500 relays, 5000 additions/sec. First stored program computer: EDSAC (Electronic Delay Storage Automatic Calculator). First stored program computer: EDSAC (Electronic Delay Storage Automatic Calculator). The Second Generation, : Discrete Transistors. (e.g IBM 7000 series, DEC PDP-1) (e.g IBM 7000 series, DEC PDP-1) The Third Generation, : Small and Medium- Scale Integrated (SSI, MSI) Circuits. (e.g. IBM 360 mainframe) The Fourth Generation, 1975-Present: The Microcomputer. VLSI-based Microprocessors.

74 Hierarchy of Computer Architecture I/O systemInstr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware Datapath & Control Layout Software Hardware Software/Hardware Boundary High-Level Language Programs Assembly Language Programs Microprogram Register Transfer Notation (RTN) Logic Diagrams Circuit Diagrams Machine Language Program

75 Summary Logic Gates AND, OR, NOT NAND NOR Drawing Logic Circuit Analysing Logic Circuit Given a Boolean expression, draw the circuit. Given a circuit, find the function. Implementation of a Boolean expression using these Universal gates. Implementation of SOP and POS Expressions Positive and Negative Logic Concept of Minterm and Maxterm

76 End of file


Download ppt "CT455: Computer Organization Logic gate. Lecture 4: Logic Gates and Circuits Logic Gates Logic Gates Logic Gates Logic Gates The Inverter The Inverter."

Similar presentations


Ads by Google