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ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA - 1 - Interconnect Working Group Whats up with wires? 14 July 2010 San Francisco USA Christopher.

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Presentation on theme: "ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA - 1 - Interconnect Working Group Whats up with wires? 14 July 2010 San Francisco USA Christopher."— Presentation transcript:

1 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Interconnect Working Group Whats up with wires? 14 July 2010 San Francisco USA Christopher Case

2 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA ITWG Regional Chairs US Christopher Case US Christopher Case Japan Tomo Nakamura Hideki Shibata Japan Tomo Nakamura Hideki Shibata Europe Hans-Joachim Barth Alexis Farcy Europe Hans-Joachim Barth Alexis Farcy Korea Hyeon-Deok Lee Sibum Kim Korea Hyeon-Deok Lee Sibum Kim Taiwan Douglas CH Yu Taiwan Douglas CH Yu

3 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Partial List of Contributors Shuhei Amakawa Nobuo Aoi Sitaram Arkalgud Lucile Arnaud Koji Ban Hans-Joachim Barth Eric Beyne Christopher Case Chung-Liang Chang Hsien-Wei Chen Gilheyun Choi Jinn-P. Chu Mike Corbett Alexis Farcy Paul Feeney Masayuki Hiroi Harold Hosack Masayoshi Imai Raymond Jao Shin-Puu Jeng Sibum Kim Mauro Kobrinsky Nohjung Kwak Hyeon Deok Lee Scott List Anderson Liu Didier Louis JD Luttmer Toshiro Maekawa Akira Matsumoto Azad Naeemi NS Nagaraj Tomoji Nakamura Yuichi Nakao Akira Ouchi Peter Ramm Rick Reidy Scott Pozder Philip Pieters Andy Rudack Larry Smith Mark Scannell Hideki Shibata Michele Stucchi Wen-Chih Chiou Weng Hong Teh Thomas Toms Manabu Tsujimura Kazuyoshi Ueno Detlef Weber Osamu Yamazaki 0710

4 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Interconnect scope Conductors and dielectrics –Starts at contacts –Metal 1 through global levels –Includes the pre-metal dielectric (PMD) Associated planarization Necessary etch, strip and cleans Embedded passives Global and intermediate TSVs for 3D Reliability and system and performance issues Needs based replaced by – scaled, equivalently scaled or functional diversity drivers.

5 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA MPU Cross-Section Dielectric Capping Layer Copper Conductor with Barrier / Nucleation Layer Pre-Metal Dielectric Tungsten Contact Plug Inter- Mediate (=M1x1) Inter- Mediate (=M1x1) Metal 1 Passivation Dielectric Etch Stop Layer ASIC Cross-Section Semi- Global (=M1x2) Semi- Global (=M1x2) Metal 1 Pitch Via Wire Via Wire Via Wire Metal 1 Pitch Global (=IMx1.5~2µm) Global (=IMx1.5~2µm) Inter- Mediate (=M1x1) Inter- Mediate (=M1x1) Metal 1 Global (=IMx1.5~2µm) Global (=IMx1.5~2µm) 1)MPU : Revised hierarchy 2)ASIC : No drastic change, however semi-global should be kept at 2 x M1 Hierarchical Cross Sections

6 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Technology Requirements Now restated and organized as General requirements –Resistivity –Dielectric constant –Metal levels –Reliability metrics Level specific requirements (M1, intermediate, global) –Geometrical Via size and aspect ratio Barrier/cladding thickness Planarization specs –Materials requirements Conductor effective resistivity and scattering effects –Electrical characteristics Delay, capacitance, crosstalk, power index

7 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Technology Drivers Expanding Traditional geometric scaling –Cost –Necessary to enable transistor scaling Performance –Dielectric constant scaling for delay, and power improvements Reliability –EM –Crosstalk Increasing value by adding functionality using CMOS- compatible solutions: –3D, optical components, sensors –Contributing to More than Moore

8 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Difficult challenges (1 of 2) Meeting the requirements of scaled metal/dielectric systems –Managing RC delay and power New dielectrics (including air gap) Controlling conductivity (liners and scattering) –Filling small features Barriers and nucleation layer Conductor deposition –Reliability Electrical and thermo-mechanical Engineering a manufacturable interconnect stack compatible with new materials and processes –Defects –Metrology –Variability

9 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Difficult challenges (2 of 2) Meeting the requirements with equivalent scaling –Interconnect design and architecture (includes multi- core benefits) –Alternative metal/dielectric assemblies 3D with TSV –Interconnects beyond metal/dielectrics 3D Optical wiring CNT/Graphene –Reliability Electrical and thermo-mechanical Engineering a CMOS-compatible manufacturable interconnect system –Non-traditional materials (for optical, CNT etc.) –Unique metrology (alignment, chirality measurements, turning radius etc)

10 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Effective Dielectric Constant; keff Year of 1st Shipment ITRS1999 ITRS2001 ITRS2005 ITRS2003 Before 2001, unreasonable RM without logical basis Before 2001, unreasonable RM without logical basis ITRS Historical Transition of ITRS Low-k Roadmap 2009 decreased max bulk by no significant change on eff in no changes 2009 decreased max bulk by no significant change on eff in no changes Since 2003, based on wiring capacitance calculation of three kinds of dielectric structures and validated against publications 2009 Summer Conference

11 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Low k or nothing? Air gap architectures will be required for bulk <2.0 No viable materials expected to be available. Mechanical requirements easier to achieve with air-gaps. End of the material solution and the beginning of an architecture solution. Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Interlevel metal insulator – bulk dielectric constant (κ) Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Interlevel metal insulator – bulk dielectric constant (κ) 1.9– – –1.7

12 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Air Gap Pictures (top left, clockwise): NXP, IBM, Panasonic, TSMC Approaches Creation of air gaps with non-conformal deposition Removal of sacrificial materials after multi-level interconnects

13 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Barrier/Nucleation/Resistivity ALD barrier processes and metal capping layers for Cu are lagging in introduction – key challenge Resistivity increases due to scattering and impact of liners No known practical solutions Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Barrier cladding thickness Metal 1 (nm) Conductor effective resistivity (µ cm) Cu Metal Year of Production MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) Barrier cladding thickness Metal 1 (nm) ` Conductor effective resistivity (µ cm) Cu Metal

14 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Cu Contact Transition Prospective 5% of total parasitic resistance for contact resistance (agreed with PIDS, FEP and INTC in 2008) Estimation of contact resistance used to forecast timing for Cu Target W-plug Cu-plug 45/40nm32/28nm22/20nm marginal W-plug will be applicable until 22/20nm node at Cu-plug will be able to satisfy the requirement beyond 15/14nm node after OK Year Resistance ( /contact) 15nm NG 65~54nm45~32nm27~21nm19nm~ITRS Commercial Assumption Aspect ratio=5.5 Barrier for W-plug Barrier for Cu-plug

15 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Year J max J EM Wire current limit – width dependence The color boundaries may actually be width-dependent. –Hu et al., Microelectronics Reliability, vol.46, pp , J max will increase with frequency and reducing cross-section, while J EM will scale with the product w*h according to EM lifetime dependence on wiring width J max 2008 J max Update 2010 To be revised

16 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA H. Shibata added published data based on Yokogawa et. Al. IEEE Trans on ED.2008 EM Lifetime Improvement Ratio Normalized Resistance Increase Ratio CuSiN CuAl CoWP CuSiN 1 CuSiN 2 CuGeN CuSi(N) + Ti-BM CoWP-Cap Si Al CuAl-Alloy CuSiN-Cap CuGeN-Cap Ge CuSiN-Cap+Ti Metal Capping Various lifetime improvement approaches against the resistivity increase

17 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA High Density TSV Roadmap or enabling terabits/sec at femtojoules/bit The Interconnect perspective - examples: –High bandwidth/low energy interfaces between memory and logic –Heterogeneous integration with minimal parasitics (analog/digital, mixed substrate materials, etc.) –Re-architect chip by placing macros (functional units) on multiple tiers (wafers) and connect using HD TSVs Defined a 3D interconnect hierarchy TSV dimensions Minimum contact pitches Overlay accuracy –Described process modules

18 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Emerging Interconnect Changes OUT: Air gaps Process Module Section Increasing maturity of integrated air gap solutions 3D Process Module and Architecture Sections 3D with TSVs nearing production IN: Focus on Cu Replacements Section on Native Device Interconnects Identified need to jointly consider switch and interconnect properties of new switch options

19 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA All roads lead to C? AlCuC GeSiC

20 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Native Device Interconnects Nanowires GNRs CNTs Spin Transport Doped NWs require silicidation for lengths > 1µm Multi-fanouts are very difficult Serial, multi-input AND gates are easy Multi-fanouts are easy Multi-layer routability incurs quantum resistance Diffusion and spin wave transport are 1000 times slower than electron transport Spin relaxation lengths are ~ 1µm 1k /µm 1 M 12k mfp

21 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Potential interconnect state variables GA Tech is using a Benchmarking Approach: Define possible transportation mechanisms in general Model delay and energy per bit for various transport mechanisms. Benchmark new state variables against their conventional counterpart as a function interconnect length. From Naeemi et al. Transport Mode Information Token DiffusionDirect Excitons Indirect Excitons Spin PseudoSpin DriftIndirect Exitons Spin Pseudospin Ballistic Transport (Fermi Velocity) Spin Pseudospin Spin WaveSpin EM WavesPhotons Plasmons

22 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Delay versus Length Communications of new state variables are all slow compared to conventional CMOS interconnects. Interconnect Length (Gate Pitch) Delay (ps) CMOS (Min-Size Driver) Diffusion Drift Ballistic CMOS (5x Driver) Spin Waves (10 4 m/s) Spin Waves (10 5 m/s) Two spin wave phase velocities of 10 4 (realistic) and 10 5 m/s (optimistic) are considered. Driver delay is not included for new state variables (upper bound performance)

23 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Required Area Down-Scaling Important implications at the Device and architecture levels. Novel interconnects can compete with their conventional counterparts only if the new circuits occupy smaller areas. To have smaller circuits switches must be smaller or same functions can be obtained with fewer switches. For longer interconnects larger circuit area scaling is needed. For a given area scaling, maximum circuit size with no signal conversion can be obtained. Diffusion Drift, 0.8V Ballistic Spin Waves (10 5 m/s) Interconnect Length (Gate Pitch) Needed Area Scaling A CMOS /A Post-CMOS

24 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Energy per bit For a Co 30 Fe 70 SWB, energy is taken to be 1aJ/um* * A. Khitun et al, Nanotechnology, vol. 18, no. 46, CMOS DIFFUSION DRIFT,0.8V SWB The excitation energy has been optimistically assumed to be negligible.

25 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Emerging Interconnect Summary Table Interconnect options include Cu Extensions, Cu Replacements and Native Device Interconnects OptionPotential AdvantagesPrimary Concerns Other metals (W, Ag, silicides) Potential lower resistance in fine geometries Grain boundary scattering, integration issues, reliability Nanowires Ballistic conduction in narrow lines Quantum contact resistance, controlled placement, low density, substrate interactions Carbon Nanotubes Ballistic conduction in narrow lines Quantum contact resistance, controlled placement, low density Graphene Nanoribbons Ballistic conduction in narrow films, planar growth Quantum contact resistance, control of edges, deposition and stacking Optical (interchip) High bandwidth, low power and latency, noise immunity Connection and alignment between die and package, optical /electrical conversions Optical (intrachip) Latency and power reduction for long lines, high bandwidth with WDM Benefits only for long lines, need compact components, integration issues, need WDM Wireless Available with current technology, wireless Very limited bandwidth, intra-die communication difficult, large area and power overhead SuperconductorsZero resistance interconnect, high Q passives Cryogenic cooling, frequency dependent resistance, defects, low critical current density ~Example of Approaches for Cu Replacements ~

26 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Formidable Task: Fabricating Dense Bundles of SWNTs Fabricating Bundles of Densely Packed SWNTs for interconnects has proven very challenging. Making contacts to horizontal bundles of SWNTs is very difficult. Promising progress in creating aligned isolated SWNTs by transferring SWNTs grown on sapphire to other substrates. Single SWNTs are too resistive for general purpose CMOS circuits. Y. Nishi and H.-S. Philip Wong (Stanford) 26 Young Lae Kim et al. (RPI, RICE & NorthEastern Univ

27 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Graphene – a promising interconnect option beyond Cu/Low k? Graphene Potentials Device/interconnect synergism Tunable bandgap Ballistic transport for > 10 m Planar technology Excellent J max Potential CVD deposition process Graphene Areas for Research Layer to layer coupling/scattering Low T CVD deposition Effective bandgap control

28 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Prognosis Interconnects can impose major limits on both charge and non-charge based devices. Most transport mechanisms for novel state-variables are relatively slow. For the same speed, the new circuits must be smaller in terms of physical area. The new devices must offer better delay-energy trade-offs compared with conventional CMOS devices. Interconnects have important implications at the device, circuit and architecture levels.

29 ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA Summary D and air gaps moved out of emerging sections Low-k – unchanged – second time in 10 years –Air gaps expected to be solution for k bulk <2.0 J max current limits are width dependent - a new concern Barriers and nucleation layers are a critical challenge –ALD barrier process is lagging in introduction – sub 1 nm specs –Ru hybrid approaches proliferating –Capping metal for reliability improvement New Interconnect 3D TSV roadmap tables Cu contact need expected >2013 Emerging Interconnect Properties being developed First principle consideration of interconnects properties for new switches – CNT, graphene, nanowires etc.


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