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ITRS Roadmap Design + System Drivers Makuhari, December 2007 Worldwide Design ITWG Good morning. Here we present the work that the ITRS Design TWG has.

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Presentation on theme: "ITRS Roadmap Design + System Drivers Makuhari, December 2007 Worldwide Design ITWG Good morning. Here we present the work that the ITRS Design TWG has."— Presentation transcript:

1 ITRS Roadmap Design + System Drivers Makuhari, December 2007 Worldwide Design ITWG
Good morning. Here we present the work that the ITRS Design TWG has pursued in 2007, and describe the continuation of this work into our 2008 strategy.

2 Overview 1. More concise, precise design technology roadmap 2
Overview 1. More concise, precise design technology roadmap 2. More comprehensive set of drivers for diversified, system-driven industry 2007 More Than Moore analysis + iNEMI 2006 Consumer Stationary, Portable, and Networking Drivers 2005 Consumer stationary and Portable Drivers 2004 Consumer Portable Driver As this slides summarizes, we have been following a consistent successful strategy in the last years. There are two components to this strategy. First, we have been assembling a quantified Design Technology roadmap, one that resembles in structure the other non-Design chapters in our roadmap, a necessary improvement. Second, we have been assembling a comprehensive set of system drivers aligned by segment, thereby mirroring the increasing segmentation in the semiconductor industry. As you can see in the chart, we have been successful. Our Design Technology roadmap includes numerous metrics and carefully matching text sections in the Design Chapter. Our System Drivers chapter has been adding several new drivers over the last few years. This work, however, needs to continue and be updated yearly. Lastly, in 2007 we have started adding explicit content about More Than Moore and have started aligning our chip roadmap with the leading system roadmaps, specifically iNEMI. System Drivers Chapter Driver study Revised Design Technology Metrics Revised Design Technology metrics Explore Design metrics Design Technology metrics Design Chapter

3 This Talk: 2007 Details 2007 2006 2005 2004 More Than Moore analysis
+ iNEMI 2006 Consumer Stationary, Portable, and Networking Drivers 2005 Consumer stationary and Portable Drivers 2004 Consumer Portable Driver Let’s go over our 2007 work, and how it drives into 2008 System Drivers Chapter Driver study Revised Design Technology Metrics Revised Design Technology metrics Explore Design metrics Design Technology metrics Design Chapter

4 ITRS Design + System Drivers
2007 More Than Moore analysis + iNEMI 2006 Consumer Stationary, Portable, and Networking Drivers 2005 Consumer stationary and Portable Drivers 2004 Consumer Portable Driver Let’s take a look at the Design Technology Roadmap, which over the last few years was formed. Unique in our industry by the way. System Drivers Chapter Driver study Revised Design Technology Metrics Revised Design Technology metrics Explore Design metrics Design Technology metrics Design Chapter

5 Design Chapter Sections: Improved, More Concise Format
Target of 1/4 to 1/3 reduction of page count Three main portions: (a) Requirements table 1-2 pages. Includes subsection description, metric definitions, rationale for each number. Number of metrics:  10 (more subject to approval) (b) Solutions table 1 to 1.5 pages. Includes definitions for each solution, and rationale for each solution. Number of solutions:  10 (more subject to approval) (c) Mapping from challenges to solutions Maps challenges to solutions. Does not need to be 1-to-1. Any requirements with no solutions need explanation.  1 page. While we had already assembled a Design Technology Roadmap, in 2007 we did quite a few improvements and updates. We start with the “cosmetic” ones – specifically we have made a big effort to make the chapter more concise and consistent, with every section approximately the same size, including its text and its tables.

6 Design Technology Roadmap Improved Parameter Explanations
Example: Logic / Circuit / Physical At the same time, we need to clarify very distinctly each parameter in our design technology requirement tables. As such, we have introduced fairly detailed description of most requirements in the chapter, thereby reaching a major improvement. This slide shows an example, a few requirements of the Logic/circuit/physical design section.

7 Design Technology Roadmap New Requirement-Solution Matching Tables
Example: Logic / Circuit / Physical An additional approach to improve our chapter clarity - to clarify the sometimes complex relationships between requirements and solutions, we have introduced the requirement-solution matching tables for each section in the design chapter. This slides shows an example, the Logic/circuit/physical matching table, done in 2007.

8 Design Technology Roadmap New Requirement-Solution Matching Tables
Example: Design For Manufacturability This slides shows another example, the DFM requirement-solution matching table in the design chapter.

9 New Software Design Roadmap Combined HW+SW Design Cost
NRE cost for SW design to equal HW design  until design technology for SW issues is addressed SW cost HW cost But the changes are beyond cosmetic, clarifying, and content-reducing; we have definitely introduced a key component in modern chip design, especially its impact on design technology and design productivity: SOFTWARE. This slides illustrates the impact on design productivity in terms of design cost, decoupled into software and hardware. As a roadmap, we have realized that software cost will become a major factor in design cost in the next years. However, if all predicted solutions are actually implemented, overall cost will still be roughly under control, or at least will not explode.

10 ITRS Design + System Drivers
2007 More Than Moore analysis + iNEMI 2006 Consumer Stationary, Portable, and Networking Drivers 2005 Consumer stationary and Portable Drivers 2004 Consumer Portable Driver Let’s go over the system drivers chapter, our work over the last years, and our 2008 work. System Drivers Chapter Driver study Revised Design Technology Metrics Revised Design Technology metrics Explore Design metrics Design Technology metrics Design Chapter

11 An Expanded Set of Drivers Will Direct An Increasingly Broad Industry
Fabrics 2008 2008 2006 2007 2006 2006 2008 SW ? MPU PE(DSP) Memory This is the matrix we created to show how segment-based drivers and “fabrics” (horizontal and vertical respectively in the figure) are fundamentally connected parts of our system drivers roadmap. As you can see from the colors in the figure, we have been expanding segment by segment (office -> consumer protable  consumer stationary  networking) while updating the fabrics each years. In 2008 we expect to complete our automotive driver while exploring a new FPGA/configurable driver, probably on the vertical/fabric axis. We will also explore medical and defense. AMS Medical Automotive Office Network Consumer Portable Consumer stationary Defense Markets

12 New Networking System Driver
Multi-Core/Accelerator Engine SoC - Architecture template Goals Performance Ease of use Components - On-chip fabric 32+ cores with private memory Accelerator engine app-specific Here’s the new driver for 2007, the networking driver. Critically important driver for the key design parameter of chip bandwidth while also a key driver increasingly for multi-core design, with both an explosion of specialized and general purpose cores. The slide shows our architectural template for this driver.

13 ITRS Design + System Drivers
2007 More Than Moore analysis + iNEMI 2006 Consumer Stationary, Portable, Automotive and Networking Drivers 2005 Consumer stationary and Portable Drivers 2004 Consumer Portable Driver Let’s go over our cross-chapter work (design > system drivers). First, More than moore, second, alignment with system roadmaps, specifically iNEMI. System Drivers Chapter Driver study Revised Design Technology Metrics Revised Design Technology metrics Explore Design metrics Design Technology metrics Design Chapter

14 Design Solution Inventory
Classification of 50+ design technology solutions 1. Supporting Moore’s Law – More Moore (geometric scaling) 2. Extending Moore’s Law – More Moore (equivalent scaling) 3. Beyond Moore’s Law – More Than Moore (functional diversification) Example: System-Level Design Solutions More Moore More Moore More Than Moore This slide is an expansion of what we described before. We remind what Geo scaling, equivalent scaling, and functional diversification are. Then we see a few example of how we have been doing the classification / inventory.

15 Design Solution Inventory
Many contributions beyond dimensional scaling More Moore (equivalent scaling) More Than Moore (functional diversification) Inventory of 50+ Design Solutions More Moore (geometric scaling) Another view on the data – strong impact of traditional Moore’s law on design, yet design technology that enables or leverages equivalent scaling (e.g. leveraging new devices and materials) and functional diversification (e.g. SIP tools, HW/SW co-design, Usage of non-digital-CMOS devices) is growing rapidly in importance (more than half of solutions already). More Moore (equivalent scaling) More Than Moore (functional diversification)

16 Design-Driven Semiconductor Innovation
Domain- / Market-Independent Inventory of 50+ Design Solutions  Reveals impact of More Than Moore on key design phases The following chart shows some of the results. As you can see, as we go through the Design chapter sections, from high-level design (system level) to the lowest level (DFM, or interface with manufacturing), the importance of “More than Moore” or “Functional diversification” design technologies seems to wane, which makes certain sense, as it is at the highest level that design most of the tools and techniques used to combine diverse SoC or SIP blocks. Equivalent scaling (More Moore) and geometric scaling (Moore) are obviously very important at lower levels of abstraction, where we deal with typically a single type of fabric (e.g. CMOS transistors or standard cells)

17 More Than Moore Impact: “Pilot Example” Focused on design levers, e. g
More Than Moore Impact: “Pilot Example” Focused on design levers, e.g., multi-core Consumer Stationary Driver Normalized performance 2006 2008 2010 2012 2014 2016 2018 2020 48% CAGR Performance 30% CAGR # cores 14-17% CAGR Device speed A possibly helpful view comes from examining the consumer system driver in one of our chapters. Specifically one can quickly see that only a small increase in performance comes directly from device scaling, which itself is becoming more and more difficult. Indeed, multi-core techniques, for example, which do not simply leverage faster, smaller devices, and can only extract part of the latent paralelism, are increasing in importance in determining overall performance measured and power consumed by a chip.

18 ITRS Design + System Drivers
2007 More Than Moore analysis + iNEMI 2006 Consumer Stationary, Portable, Automotive and Networking Drivers 2005 Consumer stationary and Portable Drivers 2004 Consumer Portable Driver Let’s now look at the system alignment of this work. Our group is the only group focused on design, we’re also the closest to the system level, i.e. SoC, SIP, boards and boxes! System Drivers Chapter Driver study Revised Design Technology Metrics Revised Design Technology metrics Explore Design metrics Design Technology metrics Design Chapter

19 ITRS-iNEMI Domain Space
(emulators) Market requirements ITRS (Drivers) Tech requirements Here’s how we relate to system level roadmaps. We focus on chips, they focus on systems. We focus on technology requirements, the focus on market requirements. This is not 100% accurate, we do both overall with each other – that’s actually an opportunity. As we increase our system driver roadmap, we need to link it directly to the system level roadmap information which is also segment based in iNEMI. Chip level System level

20 1st Alignment Between Chip and System Roadmaps Consumer Portable pilot, focused on power/energy
~10 parameters to be aligned We created a ITRS-iNEMI cross-designt team. To keeps things focused and effective, we focused only on the consumer portable driver, and we tried to align it to the portable emulator from the iNEMI roadmap. We also focused even more – we looked for parameters related to power and energy, a critical metric for all of us. As the few green colors indicate, it was quite difficult due to semantic differences, different work focus between roadmaps, and imcomplete emulator data.

21 iNEMI-ITRS ITRS Portable System Model
Application processor Baseband processor Processing POWER Memory NAND Flash Memory Wireless Flash Memory / Flash COST Other (MEMS, etc.) Audio / video codec Power mgt. The additional issue is the lack of architectural templates at the system level. As a result, we do not always have a clear view of what chips (which we focus on) exist in the systems (which iNEMI focused on).We intend to work on helping iNEMI with creating them in 2008, as advisors. I/O controller I/O transceivers Analog / I/O NOISE SENSITIVITY

22 iNEMI vs. ITRS Power Reconciliation Top-10 Parameters to be Reconciled
But we were succesful at creating a set of rouchly 10 aligned metrics, out of which a couple were especially useful as they had somewhat similar semantics and actual data. Go over some of the metrics here to make our points…

23 iNEMI vs. ITRS (System vs. Chip) Power Parameters Comparison
ITRS stuck between lower voltages and higher power trends Voltage supply trends Power trends iNEMI portable emulator ITRS consumer driver iNEMI portable emulator Two interesting findings from a couple of these aligned metrics. First, system level voltages seems to be going down quite fast, compared with chip supplies (primarily because chips are not properly scaled, to increase performance). The room seems to be closing, which will make it ever more difficult to regulate these voltages on and off chip. Second, chip power is growing a lot faster than the “hottest chip” system power allowed in iNEMI. As a result, our power crisis get yet another boost, this time because of another system level issue. ITRS consumer driver

24 Summary 1. More concise, precise design technology roadmap 2
Summary 1. More concise, precise design technology roadmap 2. More comprehensive set of drivers for diversified, system-driven industry 2007 More Than Moore analysis + iNEMI 2006 Consumer Stationary, Portable, Automotive and Networking Drivers 2005 Consumer stationary and Portable Drivers 2004 Consumer Portable Driver To summarize, we have successfully created a first version of a quantified design technology roadmap, and are almost done at creating a complete set of segment-based system drivers to guide our industry, including DT suppliers, chip houses and IP providers, DFM teams, and even foundries. System Drivers Chapter Driver study Revised Design Technology Metrics Revised Design Technology metrics Explore Design metrics Design Technology metrics Design Chapter

25 Looking to 2008: Design Refinement of existing metrics
Software productivity Design for Test New metrics DFM (CD variability roadmap) System-level tools SiP tools More than Moore Update count of MtM solutions as part of all solutions Increase amount of SiP + board related metrics For the design chapter, in 2008, we will focus on three main areas: refining existing metrics, introducing new metrics, and extending our More and Moore work. Go over the bullets one by one… 25

26 Looking to 2008: System Drivers
New drivers FPGA / reconfigurable fabric (2008) Automotive (2008) Medical, Defense (2009) Refinement of existing drivers Consumer portable /stationary (power limits) MPU (power-limited) More than Moore Further alignment with iNEMI: consumer portable Start “board-level” architecture template For the system driver chapter, in 2008, we will focus on three main areas: finalizing the list of segment drivers, and furthering our more than moore work, at the system level, creating templates that align with system levels roadmaps such as iNEMI. 26

27 Grand Challenges for Design and ITRS
Near-Term Design Productivity Overall (HW + SW) Power Management Total power (active and leakage) Design for Manufacturability Modeling of variability + yield-aware optimizations Long-Term Software and system-level (heterogeneous multi-core) Multi-technology integration Leakage and reliability Design for Manufacturability and Yield Integration of design for yield / mfg / test This is a reminder that the fundamental 3 areas of concern are still very much alive in our roadmap and expected to drive our efforts for the next years.


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