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Work in Progress – Do Not Publish! 1 Summer Public Conference ORTC 2010 Update Messages A. Allan, 07/14/10, Rev 8.

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Presentation on theme: "Work in Progress – Do Not Publish! 1 Summer Public Conference ORTC 2010 Update Messages A. Allan, 07/14/10, Rev 8."— Presentation transcript:

1 Work in Progress – Do Not Publish! 1 Summer Public Conference ORTC 2010 Update Messages A. Allan, 07/14/10, Rev 8

2 Work in Progress – Do Not Publish! 2 Summer Update to the 4/3 Italy 2009 ITRS ORTC 1)ORTC Model Proposals to TWGs for TWG Interdependency Preparation for other ORTC section features: 1)Beyond CMOS timing unchanged in 2010 for ERD/ERM early research and transfer to PIDS; however need for continued discussion about transfer of III/V Gate Material technology in 2011 Renewal 2)Logic Equivalent Scaling Roadmap Timing Update underway, and ongoing discussion of alignment of node and dimensional Trends for 2011 Renewal 3)New More than Moore (MtM) white paper draft review and discussion underway for 2011 ITRS Renewal impact and added to the ITRS website at 2)MPU contacted M1 1)Unchanged for 2010 [validated by FEP data] 2)2-year cycle trend through )Cross-over DRAM M1 2010/45nm 4)Smaller 60f 2 SRAM 6t cell Design Factor 5)Smaller 175f 2 Logic Gate 4t Design Factor 6)Proposal from Taiwan [2011 Renewal]: Design TWG evaluate 1-year pull-in of M1 3)DRAM contacted M1 1)Unchanged for 2010: Dimensional M1 half-pitch trends remain unchanged from 2007/08/09 ITRS; new 4f2 Design factor begins )Proposal [2011 Renewal]: 1-year pull-in of M1 and bits/chip trends; 4f2 push out 4)Flash Un-contacted Poly 1)Unchanged for 2010: 2yr cycle trend through 2010/32nm; then 3yr cycle and also added equivalent scaling bit design: 1)Inserted 3bits/cell MLC ; and delayed 4bits/cell (2 companies in production) until )Proposal [2011 Renewal]: 1-year pull-in of Poly; however 3bits/cell extended to 2018; 4bits/cell delay to 2019

3 Work in Progress – Do Not Publish! 3 5)Unchanged for 2010 Tables: MPU GLpr – yr flat; Low operating and standby line items track changes 6)Unchanged for 2010 Tables: MPU GLph – yr flat with equiv. scaling process tradeoffs; Low operating and standby line items track changes 1)Performance targets (speed, power) on track with tradeoffs 7)Unchanged for 2010 Tables: MPU Functions/Chip and Chip Size Models 1)Utilized Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and updated cell design factors 2)ORTC line item OverHead (OH) area model, includes non-active area 3)ORTC model impact from Taiwan proposal will be evaluated for 2011 Renewal 8)DRAM Bits/Chip and Chip Size Model Unchanged for 2010 Tables - 3-year generation Moores Law doubling cycle; 1)smaller Chip Sizes (<60mm2) with 4f2 design factor included 2)ORTC model impact updating from PIDS/FEP Survey proposals will be evaluated for 2011 Renewal 9)Flash Bits/Chip and Chip Size Model Unchanged for 2010 Tables 1)2-year generation Moores Law doubling cycle; 2)growing Chip Sizes after return to 3-year technology cycle 3)ORTC model impact updating from PIDS/FEP Survey proposals will be evaluated for 2011 Renewal] 10)IRC 450mm Position: Pilot lines/2012; Production/ Unchanged for 2010; also Unchanged: double S-curve graphic in 2009 Executive Summary 1)450mm Program status and Long-Range IEM v12 Demand Update Scenario was presented by ISMI to IRC for 2011 ITRS Renewal preparation 2)ISMI believes the 450mm program is presently on track to meet ITRS Timing Italy 4/9 Update to the 12/16 Taiwan 2009 ITRS ORTC (cont.)

4 Work in Progress – Do Not Publish! Definition of the Half Pitch – unchanged [No single-product node designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables] Source: 2009 ITRS - Exec. Summary Fig 1 Poly Pitch Typical flash Un-contacted Poly FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/ Lines Metal Pitch Typical DRAM/MPU/ASIC Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/ Unchanged

5 Work in Progress – Do Not Publish! 5 Production Ramp-up Model and Technology/Cycle Timing Months Alpha Tool DevelopmentProduction Beta Tool Production Tool First Conf. Papers First Two Companies Reaching Production K 20K 200K Additional Lead-time: ERD/ERM Research and PIDS Transfer Volume (Wafers/Month) Production Ramp-up Model and Technology Cycle Timing Source: 2009 ITRS - Exec. Summary Fig 2a 2009 – Unchanged *Examples: 25Kwspm ~= 280mm2 140mm2 100mm2 70mm2

6 Work in Progress – Do Not Publish! 6 Continuing SoC and SiP: Higher Value Systems Traditional ORTC Models [Geometrical & Equivalent scaling] Scaling (More Moore) Functional Diversification (More than Moore) HV Power Passives Scaling (More Moore) 2007 ITRS Executive Summary Fig 4 New work In 2009 New in 2009: Research and PIDS transfer timing clarified Work underway to identify next storage element Online in 2008: SIP White Paper New in 2009: More than Moore White Paper More Commentary In ITWG Chapters New in 2009: Survey updates to ORTC Models Equivalent Scaling Roadmap Timing Synchronized with PIDS and FEP Source: 2009 ITRS - Executive Summary Fig WAS

7 Work in Progress – Do Not Publish! 7 Moores Law & More More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators HV Power Analog/RFPassives 130nm 90nm 65nm 45nm 32nm 22nm 16 nm. V Information Processing Digital content System-on-chip (SoC) Beyond CMOS Interacting with people and environment Non-digital content System-in-package (SiP) 2010 Update/2011 Renewal MtM Graphic Proposal from Europe IRC 2010 MtM White Paper Update [Note: iNEMI Roadmap work will Propose additional modifications and Cross-roadmap alignment work To the IRC at the July USA ITRS Meetings]

8 Work in Progress – Do Not Publish! 8 Current figure 8c in ITRS executive summary (page 69) Equivalent Scaling Process Technologies Timing WAS 2009 [Orig. Source: ITRS, European Nanoelectronics Initiative Advisory Council] (ENIAC) Source: 2009 ITRS - Exec. Summary, Fig 8c, Equivalent Scaling Process Technologies Timing PDSOI FDSOI bulk stressors + high µ SiGe materials MuGFET MuCFET Electrostatic control SiON poly high k metal Gate stack + III/V High µ Alternative Channel Matls Channel material high k [ II, etc] metal

9 Work in Progress – Do Not Publish! 9 Equivalent Scaling Process Technologies Timing Final Proposal - for 2011 work Proposed figure 8c in ITRS executive summary Metal High k Gate-stack material Bulk FDSOI Multi-gate (on bulk or SOI) Structure (electrostatic control) Channel material Metal High k 2nd generation Si + Stress S D High-µ material ? S D PDSOI Metal High k nth generation = Additional timing movement considerations for 2011 ITRS work See also PIDS, FEP, ERD, and ERM chapters text and tables for additional detail)

10 Work in Progress – Do Not Publish! 10 ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing [Example: III-V MOSFET High-mobility Channel Replacement Materials] Source: 2009 ITRS - Executive Summary Fig 2b Months Alpha Tool Development Production Beta Tool Product Tool Volume (Wafers/Month) K 20K 200K Research Transfer to PIDS/FEP (96-72mo Leadtime) First Tech. Conf. Device Papers Up to ~12yrs Prior to Product III/V Hi- gate Example: 1 st 2 Cos Reach Product First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product 2009 Unchanged

11 Work in Progress – Do Not Publish! 11 Volume Years Alpha Tool Beta Tool Tools for Pilot line 32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011 Consortium Pilot Line Manufacturing 22nm (extendable to 16nm) M1 half- pitch capable tools Development Production 450mm 32nm M1 half-pitch Pilot Line Ramp Beta Tool Production Tool 450mm Production Ramp-up Model [ 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production Ramp Curve ] Source: 2009 ITRS - Executive Summary Fig 2c 2009 Unchanged

12 Work in Progress – Do Not Publish! 12 IRC Graphic update Proposal Considerations Also 450mm Dual S-Curve and possible alignment with Node vs. Technology Trends

13 Work in Progress – Do Not Publish! ITWG Table Timing: nm45nm 32nm22nm 16nm 2009 IS ITRS DRAM M1 : 2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm MPU/hpASIC Node: 45nm 32nm 22nm 16nm 11nm 8nm 2009 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm 2009 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm 45nm32nm 22nm16nm 11nm 2009 IS ITRS Flash Poly : 54nm New for 2009 Volume Years Alpha Tool Beta Tool Tools for Pilot line 32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011 Consortium Pilot Line Manufacturing 22nm (extendable to 16nm) M1 half- pitch capable tools Development Production 450mm 32nm M1 half-pitch Pilot Line Ramp Beta Tool Production Tool 450mm Production Ramp-up Model [ 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production Ramp Curve ] Source: 2009 ITRS - Executive Summary Fig 2c 450mm Production Ramp-up Model [ 2009 ITRS Figure 2c A Typical Wafer Generation Pilot Line and Production Ramp Curve ] Versus Node/actual contacted M1 and un-contacted Poly Half-Pitch alignment 2009 WAS

14 Work in Progress – Do Not Publish! 14 Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range of the feature size (y-axis). Data are based upon capacity if fully utilized. Year Feature Size (Half Pitch) ( m) >0.7 m m m m m m <0.08 m m 2008/09 ITRS: 2.5-Year Ave Cycle for DRAM 2-Year DRAM Cycle 3-Year DRAM Cycle ; 2-year Cycle Flash and MPU 3-Year Cycle = 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target = 2009 ITRS Flash Uncontacted Poly Half Pitch Target = 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target 3-Year Cycle After 2010 for Flash; after 2013 For MPU Source: 2009 ITRS - Executive Summary Fig WAS

15 Work in Progress – Do Not Publish! 15 >0.7 m m m m m m <0.08 m m <0.06 m Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range of the feature size (y-axis). Data are based upon capacity if fully utilized. Year Feature Size (Half Pitch) ( m) 2008/09 ITRS: 2.5-Year Ave Cycle for DRAM 2-Year DRAM Cycle 3-Year DRAM Cycle ; 2-year Cycle Flash and MPU 3-Year Cycle = 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target = 2009 ITRS Flash Un-contacted Poly Half Pitch Target = 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target 3-Year Cycle After 2010 for Flash; after 2013 For MPU Source: 2009 ITRS - Executive Summary Fig 3 4Q09 SICAS Update Proposal From Furukawa-san/Japan To IRC 3/28/10 (modified by AA) Year


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