4Agenda Scope, structure and 10 year synopsis Technology requirements Difficult challengesCu resistivity effectsEnergy and performanceLow k roadmapInterconnect for memoryDRAM wiring roadmapNon-volatile interconnect requirementsBeyond metal/dielectric systems3D, optical and carbon nanotubes (CNT)3D roadmap proposalLast words
5Interconnect scope Conductors and dielectrics Associated planarization Starts at contactMetal 1 through global levelsIncludes the pre-metal dielectric (PMD)Associated planarizationNecessary etch, strip and cleansEmbedded passivesReliability and system and performance issuesEnds at the top wiring bond pads“Needs” based replaced by – scaled, equivalently scaled or functional diversity drivers
7Technology Requirements (1/2) Tables for HP MPU and ASIC plus DRAMWiring levels including “optional levels”Reliability metricsMinimum wiring/via pitches by levelPerformance figure of merit and capacitancePlanarization requirementsConductor resistivity with and without scatteringBarrier thicknessDielectric metrics including effective k (UPDATED)Crosstalk metricMetal 1 variability due to CD and scatteringPower Index
8Technology Requirements (2/2) Now restated and organized asGeneral requirementsResistivityDielectric constantMetal levelsReliability metricsLevel specific requirements (M1, intermediate, global)GeometricalVia size and aspect ratioBarrier/cladding thicknessPlanarization specsMaterials requirementsConductor effective resistivity and scattering effectsElectrical characteristicsDelay, capacitanceYou will see small adjustemnts to metal wiring ptiches per year (a few percent)And of course all the parameteres derived from these
9+ 45 Elements (Potential) The March of Materials12 Elements+ 4 Elements+ 45 Elements (Potential)
10Difficult challenges (1 of 3) Meeting the requirements of scaled metal/dielectric systemsManaging RC delay and powerNew dielectrics (including air gap)Controlling conductivity (liners and scattering)Filling small featuresLinersConductor depositionReliabilityElectrical and thermo-mechanicalEngineering a manufacturable interconnect stack compatible with new materials and processesDefectsMetrologyVariability
11Difficult challenges (2 of 3) Meeting the requirements with equivalent scalingInterconnect design and architecture (includes multi-core benefits)Alternative metal/dielectric assemblies3D with TSVInterconnects beyond metal/dielectrics3DOptical wiringCNT/GrapheneReliabilityElectrical and thermo-mechanicalEngineering a CMOS-compatible manufacturable interconnect systemNon-traditional materials (for optical, CNT etc.)Unique metrology (alignment, chirality measurements, turning radius etc)
12Difficult challenges (3 of 3) Adding functional diversityMixed technologiesSi, GaAs, HgCdTe togetherMixed signalling approachesRFPassive devicesIntelligent Interconnect (active devices, sensors, MEMS, biochips, fluidics, etc. in interconnect)Repeaters in interconnect, combined metallic/semiconducting CNT interconnectsBack-end memoryVariable resistor viaReliabilityElectrical and thermo-mechanicalEngineering a CMOS-compatible manufacturable interconnect systemNon-traditional materials III/V, II/VIDeposition (low temperature epi)Unique metrology (composition)
13Size matters2003 – the impending impact of Cu resistivity increases at reduced feature sizes (due to scattering) - first noted2004 – metrics introduced to highlight the impact of width dependent scattering on the effective resistivity and impact on RC delayModels have been refined to more accurately predict the resistivity due to changes in aspect ratio, shape and metal thicknessMetrics updated – managed architectureAdapt the same methodology for DRAM when Cu is introduced (2007)
14Size mattersMuch to the chagrin of the industry, Cu exhibits an undesirable property in that its mean free path of conduction electrons happens to be close to the dimensions of the wires that are being fabricated. As a result, scattering from sidewalls and grain boundaries will result in more resistive wires.Modeling has confirmed this behavior. The good part of the story is that the features that are the smallest are the local and intermediate wires which are shorter and have less impact on delay.Near term impact will be readily managed design community. There are efforts underway to considered doping the conductorFew published papers have shown any way to improve this suggestionIt should be noted, that the effect of scaling alone will raise the wire resistance of a minum pitch global wire (which is 1.5 times the intermediate pitch) significantly – a factor of 20XFigure From Infineon
15Dynamic PowerIncreasing concern about rising dynamic power in the interconnect stackInterconnects make a significant contribution to total dynamic powerImpacts effective k roadmapDrives reduction in parasitic capacitanceDynamic power is a key constraint for high performance MPUsAlternative interconnect technologies (optical, CNT, RF, etc.) should be performance competitive in terms of delay and powerInfluence of number of functions (N), activity (A) and frequency (F): P = (NAF)CV2
16Capacitance and Power Index P (W/GHz-cm2)M1 ½ pitchupper valuelower valueC (pF/cm)1.01.52.02.5M1 ½ pitchM1 Intermediate GlobalUsed lowest expected k valueCapacitance per unit length decreases due to decreases of the dielectric constant.However, the dynamic power per metallization layer is expected to increase despite the efforts to decrease the dielectric constant and supply voltage.
17Table 80a (“MPU and ASIC Interconnect Technology Requirements—Near-term Years”) M1_half_pitch655952454036322825Power index (W/GHz-cm2) [x]Power index = C Vdd2 a (1 GHz) ew (1 cm2)/p; p = pitch; Vdd = supply voltage; ew = wiring efficiency = 1/3; a = activity factor = 0.03.The calculated values are an approximation for the “power per GHz per cm2 of metallization layer”.This index scales with the critical parameters that determine the interconnect dynamic power.NOTES: the values provided are an average for M1, Intermediate and Global interconnects. The range of values results from the maximum and minimum effective dielectric constants.
18R and C variabilityEffect of few % variations in different variability sourcesw=80nmt =70nmMetal width± 6nmMetal thk± 4nmBarrier thk± 2nmKeff± 0.1ILD thkw=80nmt =150nmw=100nmt =200nmw=250nmt =200nm
19Integration SchemesThe low k roadmap is always a hotly debated topic. The materials industry was able to introduce materials with appropriate bulk dielectric constants but the difficulty occurred at the integration stage.There are a variety of integration approaches some of which include etch stops, capping layers, others are hybrid approaches with the different materials embeddd in the via and between lines. As you move from the left-hand scheme, that achieves the lowest effective k value, moving to the right, the added etch levels increase k effective but have better process contorl at the expense of more process steps.Homogenoeous+ optimal trench etchstop- higher keff- many dielectric interfaces(adhesion / cost !)Himi ILD without+ lowest keff+ reduced # interfaces- critical trench etchstop(heavy burden on low k -RIE)Embedded low k+ etchstop layer optional(depends on low k choices)+ reduced crosstalk- higher keff (w. trench ES)
22Low-k again! HP MPU and ASIC WasIsRealistic case in 2007~2008Aggressive case in 2007~2008StructureHomogeneousHomo w/HMHybridk(Cu D.B)4.5k(Hardmask)NA4.1k (via)2.92.7k(trench)keff3.153.27StructureHomogeneousHomo w/HMHybridk(Cu D.B)4.0k(Hardmask)NA3.0k (via)2.72.5k(trench)keff2.962.87
24DRAM Small changes in specific via and contact resistivity Contact A/R (stacked capacitor) rises to >20 in a nearby red challenge - associated with the 45 nm DRAM half pitchCu implemented in 2007Low k with an effective dielectric constant of 3.1 – 3.4 pushed back one year to 2009Plan to distinguish embedded, flash, and traditional DRAM along with alternative memory in the interconnect in the future (2009)A big question in the industry is the insertion for copper into DRAM manufacturing – this has been delayed slightly though a survey of key fabricators, and is expected in 2007Low k is already in place.Contact A/R for memory is simply listed as greater than 20 to 1, a red challenge, this would be at a half pitch of 16 nm(add BIT)
252007 DRAM Table - n+Si, p+Si and Via 1. Values for Contact and Vias are basically consistent with measured data up to2. Beyond 2009 the values are extrapolated as proposed previously by Japan TWG:Based on contact CD scaling assumption, 30 % every 2 years (factor = 0,83/year) is between compensation of width scaling (factor = 0,89/year) and area scaling (factor = 0,79/year); % every 2 years is a good approach to keep the contact Rs below a certain limit.3. Values 2010 to 2022 should stay in redCalculated values byusing the scaling factor of 0.83
26Jmax 2007 – significant changes Impact of multi-core on interconnect length distributions was discussed regarding Jmax by Japan Design TWG, qualitatively as the first step.Assuming a symmetric multi-processor core, if the technology, the clock-frequency, and the number of logic stages per a pipeline is the same, the interconnect structures at the logic-gate level will be similar, leading to no-change in Jmax in the gate level interconnects.In addition, there might not be so much change in long wires, since repeaters are inserted either for single-core or multi-core, and so the load capacitances are similar.Based on the above discussion, there might not be so much impact of multi-core on interconnect Jmax.Numerical analysis will be done by Prof. Masu’s group with their model as the second step.: Critical points for the DC pulse current, where the minimum pitch and via-size are used for high density.
27On-chip local clock (MHz) Intermediate half pitch (nm) Jmax Change in Table 80EM improvement technologies such as CuSiNx and Cu-alloy (CuAl etc.) have become manufacturable technologies.More than 20 times EM lifetime (T) improvements lead to about 5 times Jmax improvements assuming T J-2Year of Production20072008200920102011201220132014On-chip local clock (MHz)40004191439146004819504952905542Jmax (A/cm2)2.08E+63.08E+63.88E+65.15E+66.18E+66.46E+68.08E+61.06E+70.91E+61.19E+61.38E+61.58E+61.70E+61.66E+61.90E+62.11E+6WasIsWasIs1.E+061.E+071.E+08Jmax (A/cm2)Frequency (GHz)3456781.E+05Jmax (A/cm2)<<<今回の山﨑の提案>>>【白・黄・赤について】・5E6程度までは，CuSiN（In-situ Dielectric），Cu-AlloyでOKであり，量産技術のめどは立っているので白レンガ．・1E7メタルキャップを想定しているので，チューニングで必要で黄レンガ．【水色・白・ハッチについて】・ CuSiN（In-situ Dielectric）は2008年には解のひとつとして使われなければならないので，08年からPotential Solutionの白．・メタルキャップは，同様に11年から使われるため，ここから白．・いずれも使われ始める２年間は，白のQual/Pre-Proと定義してしまう．これをあらわすと次のページのようになる．1.E+052040608010020406080100Intermediate half pitch (nm)Intermediate half pitch (nm)
28Multi-core Impact on Interconnect Wiring lengths changeCritical path reduced (in core)Mechanical integrity challenges will changeJmax changesHierarchical structure may no longer be necessaryConverge to more fine pitch local/intermediate wiresPower and ground delivered through gridGlobal delay challenge relaxed3D may include multi-coreNeed to consider splitting metrics into:In-core (intra-tile) and Inter-core (inter-tile)New bandwidth requirementsDPEDPEDPEDPEDPEDPEDPEDPEDPEDPEDPEDPEDPEDPEDPEDPEMainProcessorMainProcessorIO- Memory IF & Chip-to-Chip IF -Figure From ITRS 2006 Design TWG
29Emerging Interconnect (1/2) Use geometry3DAir gapUse different signaling methodsSignal designSignal coding techniques Use innovative design and package optionsInterconnect - centric designPackage intermediated interconnect Chip-package co-design Figure From StanfordThe working group has quietly begun to address what is often referred to as beyond the roadmap, or after copper/low interconnect needs. This is referred to as emerging interconnect.Nearer term approaches with low risk is the use of air- gaps.3D integration does not require the creation of a new material set, as optical interconnect does, but will be a complex and challenging system to implement.
30Emerging interconnect (2/2) Use different physicsOptics (waveguides, emitters, detectors, free space, trans-impedance amps, modulators)RF/microwaves (transmitters, receivers, free space, waveguides)Terahertz photonicsRadical solutionsNanowires/nanotubes/grapheneMoleculesSpintronicsQuantum wave functions One can use different propagation waves from microwave through near optical, all difficult.And of course it is always exciting to conceive of the role carbon nanotiubeso nano wire,, even self assembly.It is difficult to forecast inthis area but as the leading candidates from these areas are identified by a group led by Harodl Hosack of the SRC, initail roadmaps will be created.In the meantime, the introduction and rapid adoption of multi-c ore architecture for microprocessor has a big impact of the global delay challenge.
31From low-k to no k - air gaps Introduction of air gap architecturesCreation of air gaps with non-conformal depositionRemoval of sacrificial materials after multi-level interconnectsValues of effective k-value down to 1.7 with low crosstalk levelsLocalized air gaps to maintain good thermal and mechanical propertiesUltra-low k and Air gap (k<1.7) (CVD and Spin-on)Gaps in the dielctic, the nemesis of the dielctri cdepositoin engineerr in the in the aluminum ear are now being resurrected and featured as a soltiuon.We have to go back and find those bad process tools that came before HDP CVD.Seroulsyl, though, air gaps are a very realisticimprovement.Localized airgaps can also help by maiting good thermal conductivey and better mecahincl sternth theran a sub k=2 bulk deielctric
32Hypothetical On-die Optical Interconnects with WDM Wavelength specific modulator…s1s1s2s2s3s2Waveguides4s4s4s5s6s6Intel Technology Journal, Volume 8, Issue 2, 2004
33High Density 3D Integration Through silicon via (TSV)ReliabilityPhysical metrics (pitch, diameter, density)Alignment toleranceBond layerInterfacial defect densityAdhesionList of “Difficult Challenges”, e.g. TSV processes, alignment, low k impact on TSV, etc.
352007 last words Metal 1 design rule concerns Staggered contacted pitch used for definition68 nm half pitch for 2007High performance MPU pitches scaling at ~0.75/2 years until 2009Returning to 0.7/3 years 2010Convergence of MPU/ASIC and DRAM pitch in 2010Commonality in the back-end (Cu based)
36Summary of Notable 2007 changes Low-k slowdownNew range for bulk k and keffNew Technology IntroductionALD barrier processes and metal capping layers for Cu are lagging in introduction.No solutions seen for Cu resistivity risePower MetricCapacitance per unit length decreases due to decreases of the dielectric constant.The dynamic power is expected to increase because of the increased number of metallization layers, larger chip size and increased frequency.
37Last words Must manage the power envelope More Moore More than Moore Must continue to meet requirements of scaled metal/dielectric systems while developing CMOS-compatible equivalent scaling solutionsCu resistivity impact real but manageablematerials solutions alone cannot deliver performance - end of traditional scalingMore than Mooreintegrated system approach requiredFunctional diversity enhances valuePower is a problem, heat is a problem, performance variability is a problem, complexity is a problemThere are many materials that are introduced from cobalt caps to enhanced reliability to ruthenium seeds for electrochemical deposition, but these materials do not solve3 global signal delay challenges.This is the end of traditional scaling – you may have heard the phrase equivalent scaling used. Here that means a more more integrated approach with design and packaging will deliver the expected performance.