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Interconnect Working Group

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Presentation on theme: "Interconnect Working Group"— Presentation transcript:

1 Interconnect Working Group
2007 Edition 5 December 2007 Makuhari, Japan Christopher Case The Linde Group

2 ITWG Regional Chairs Japan Hiroshi Miyazaki Masayuki Hiroi Taiwan
Douglas CH Yu US Christopher Case Robert Geffken Europe Hans-Joachim Barth Alexis Farcy Korea Hyeon-Deok Lee Sibum Kim

3 Partial List of Contributors
Robert Geffken Hans-Joachim Barth Alexis Farcy Harold Hosack Paul Feeney Ken Monnig Rick Reidy Mauro Kobrinsky Hideki Shibata Kazuyoshi Ueno Michele Stucchi Susan Vitkavage Eiichi Nishimura Mandeep Bamal Quingyuan Han Robin Cheung Didier Louis Katsuhiko Tokushige Masayoshi Imai Greg Smith Detlef Weber Anderson Liu Scott Pozder Osamu Yamazaki Hiroshi Miyazaki Masayuli Hiroi Manabu Tsujimura Nohjung Kwak Hyeon Deok Lee Yuji Awano Sibaim Kim Lucile Arnaud JD Luttmer Sitaram Arkalgud Azad Naeemi Dirk Gravesteijn NS Nagaraj Mike Mills Skip Berry Gunther Schindler Chung-Liang Chang Tomoji Nakamura Christopher Case Remove “Kenichi Nishi” , add “Anderson Liu”

4 Agenda Scope, structure and 10 year synopsis Technology requirements
Difficult challenges Cu resistivity effects Energy and performance Low k roadmap Interconnect for memory DRAM wiring roadmap Non-volatile interconnect requirements Beyond metal/dielectric systems 3D, optical and carbon nanotubes (CNT) 3D roadmap proposal Last words

5 Interconnect scope Conductors and dielectrics Associated planarization
Starts at contact Metal 1 through global levels Includes the pre-metal dielectric (PMD) Associated planarization Necessary etch, strip and cleans Embedded passives Reliability and system and performance issues Ends at the top wiring bond pads “Needs” based replaced by – scaled, equivalently scaled or functional diversity drivers

6 Typical MPU cross section
Passivation Passivation Dielectric Dielectric Wire Wire Etch Stop Layer Etch Stop Layer Via Via Dielectric Capping Layer Dielectric Capping Layer Copper Conductor with Copper Conductor with Barrier/Nucleation Layer Barrier/Nucleation Layer Global Global Intermediate Intermediate Metal 1 Metal 1 Pre Pre - - Metal Dielectric Metal Dielectric Contact Plug Metal 1 Pitch Metal 1 Pitch

7 Technology Requirements (1/2)
Tables for HP MPU and ASIC plus DRAM Wiring levels including “optional levels” Reliability metrics Minimum wiring/via pitches by level Performance figure of merit and capacitance Planarization requirements Conductor resistivity with and without scattering Barrier thickness Dielectric metrics including effective k (UPDATED) Crosstalk metric Metal 1 variability due to CD and scattering Power Index

8 Technology Requirements (2/2)
Now restated and organized as General requirements Resistivity Dielectric constant Metal levels Reliability metrics Level specific requirements (M1, intermediate, global) Geometrical Via size and aspect ratio Barrier/cladding thickness Planarization specs Materials requirements Conductor effective resistivity and scattering effects Electrical characteristics Delay, capacitance You will see small adjustemnts to metal wiring ptiches per year (a few percent) And of course all the parameteres derived from these

9 + 45 Elements (Potential)
The March of Materials 12 Elements + 4 Elements + 45 Elements (Potential)

10 Difficult challenges (1 of 3)
Meeting the requirements of scaled metal/dielectric systems Managing RC delay and power New dielectrics (including air gap) Controlling conductivity (liners and scattering) Filling small features Liners Conductor deposition Reliability Electrical and thermo-mechanical Engineering a manufacturable interconnect stack compatible with new materials and processes Defects Metrology Variability

11 Difficult challenges (2 of 3)
Meeting the requirements with equivalent scaling Interconnect design and architecture (includes multi-core benefits) Alternative metal/dielectric assemblies 3D with TSV Interconnects beyond metal/dielectrics 3D Optical wiring CNT/Graphene Reliability Electrical and thermo-mechanical Engineering a CMOS-compatible manufacturable interconnect system Non-traditional materials (for optical, CNT etc.) Unique metrology (alignment, chirality measurements, turning radius etc)

12 Difficult challenges (3 of 3)
Adding functional diversity Mixed technologies Si, GaAs, HgCdTe together Mixed signalling approaches RF Passive devices Intelligent Interconnect (active devices, sensors, MEMS, biochips, fluidics, etc. in interconnect) Repeaters in interconnect, combined metallic/semiconducting CNT interconnects Back-end memory Variable resistor via Reliability Electrical and thermo-mechanical Engineering a CMOS-compatible manufacturable interconnect system Non-traditional materials III/V, II/VI Deposition (low temperature epi) Unique metrology (composition)

13 Size matters 2003 – the impending impact of Cu resistivity increases at reduced feature sizes (due to scattering) - first noted 2004 – metrics introduced to highlight the impact of width dependent scattering on the effective resistivity and impact on RC delay Models have been refined to more accurately predict the resistivity due to changes in aspect ratio, shape and metal thickness Metrics updated – managed architecture Adapt the same methodology for DRAM when Cu is introduced (2007)

14 Size matters Much to the chagrin of the industry, Cu exhibits an undesirable property in that its mean free path of conduction electrons happens to be close to the dimensions of the wires that are being fabricated. As a result, scattering from sidewalls and grain boundaries will result in more resistive wires. Modeling has confirmed this behavior. The good part of the story is that the features that are the smallest are the local and intermediate wires which are shorter and have less impact on delay. Near term impact will be readily managed design community. There are efforts underway to considered doping the conductor Few published papers have shown any way to improve this suggestion It should be noted, that the effect of scaling alone will raise the wire resistance of a minum pitch global wire (which is 1.5 times the intermediate pitch) significantly – a factor of 20X Figure From Infineon

15 Dynamic Power Increasing concern about rising dynamic power in the interconnect stack Interconnects make a significant contribution to total dynamic power Impacts effective k roadmap Drives reduction in parasitic capacitance Dynamic power is a key constraint for high performance MPUs Alternative interconnect technologies (optical, CNT, RF, etc.) should be performance competitive in terms of delay and power Influence of number of functions (N), activity (A) and frequency (F): P = (NAF)CV2

16 Capacitance and Power Index
P (W/GHz-cm2) M1 ½ pitch upper value lower value C (pF/cm) 1.0 1.5 2.0 2.5 M1 ½ pitch M1 Intermediate Global Used lowest expected k value Capacitance per unit length decreases due to decreases of the dielectric constant. However, the dynamic power per metallization layer is expected to increase despite the efforts to decrease the dielectric constant and supply voltage.

17 Table 80a (“MPU and ASIC Interconnect Technology Requirements—Near-term Years”)
M1_half_pitch 65 59 52 45 40 36 32 28 25 Power index (W/GHz-cm2) [x] Power index = C Vdd2 a (1 GHz) ew (1 cm2)/p; p = pitch; Vdd = supply voltage; ew = wiring efficiency = 1/3; a = activity factor = 0.03. The calculated values are an approximation for the “power per GHz per cm2 of metallization layer”. This index scales with the critical parameters that determine the interconnect dynamic power. NOTES: the values provided are an average for M1, Intermediate and Global interconnects. The range of values results from the maximum and minimum effective dielectric constants.

18 R and C variability Effect of few % variations in different variability sources w=80nm t =70nm Metal width ± 6nm Metal thk ± 4nm Barrier thk ± 2nm Keff ± 0.1 ILD thk w=80nm t =150nm w=100nm t =200nm w=250nm t =200nm

19 Integration Schemes The low k roadmap is always a hotly debated topic. The materials industry was able to introduce materials with appropriate bulk dielectric constants but the difficulty occurred at the integration stage. There are a variety of integration approaches some of which include etch stops, capping layers, others are hybrid approaches with the different materials embeddd in the via and between lines. As you move from the left-hand scheme, that achieves the lowest effective k value, moving to the right, the added etch levels increase k effective but have better process contorl at the expense of more process steps. Homogenoeous + optimal trench etchstop - higher keff - many dielectric interfaces (adhesion / cost !) Himi ILD without + lowest keff + reduced # interfaces - critical trench etchstop (heavy burden on low k - RIE) Embedded low k + etchstop layer optional (depends on low k choices) + reduced crosstalk - higher keff (w. trench ES)

20 Low-k Trend (2003-2006 IITC, IEDM, VLSI, AMC)
 90 nm(2005-)    65 nm(2007-)    45 nm(2010-) CVD SiOC DD (k=2.9) CVD SiOC DD (k=3.0) CVD SiOC DD (k=2.75) CVD SiOC DD (k=2.45) CVD SiOC DD (k=2.5) CVD SiOC hybrid DD (k=2.2/2.5) NCS/CVD SiOC stack DD (k=2.25/2.9) NCS/NCS stack DD (k=2.25/2.25) PAr/SiOC hybrid DD (k=2.6/2.5) P-PAr/p-SiOC hybrid DD (k=2.3/2.3) CVD SiOC DD (k=2.65) CVD SiOC stack DD (k=2.6/3.0) CVD SiOC DD (k=2.6)? Intel IBM TSMC Renesas Fujitsu Toshiba Sony NECEL

21 Low-k update

22 Low-k again! HP MPU and ASIC
Was Is Realistic case in 2007~2008 Aggressive case in 2007~2008 Structure Homogeneous Homo w/HM Hybrid k(Cu D.B) 4.5 k(Hardmask) NA 4.1 k (via) 2.9 2.7 k(trench) keff 3.15 3.27 Structure Homogeneous Homo w/HM Hybrid k(Cu D.B) 4.0 k(Hardmask) NA 3.0 k (via) 2.7 2.5 k(trench) keff 2.96 2.87

23 Low-k Roadmap Table Update

24 DRAM Small changes in specific via and contact resistivity
Contact A/R (stacked capacitor) rises to >20 in a nearby red challenge - associated with the 45 nm DRAM half pitch Cu implemented in 2007 Low k with an effective dielectric constant of 3.1 – 3.4 pushed back one year to 2009 Plan to distinguish embedded, flash, and traditional DRAM along with alternative memory in the interconnect in the future (2009) A big question in the industry is the insertion for copper into DRAM manufacturing – this has been delayed slightly though a survey of key fabricators, and is expected in 2007 Low k is already in place. Contact A/R for memory is simply listed as greater than 20 to 1, a red challenge, this would be at a half pitch of 16 nm(add BIT)

25 2007 DRAM Table - n+Si, p+Si and Via
1. Values for Contact and Vias are basically consistent with measured data up to 2. Beyond 2009 the values are extrapolated as proposed previously by Japan TWG: Based on contact CD scaling assumption, 30 % every 2 years (factor = 0,83/year) is between compensation of width scaling (factor = 0,89/year) and area scaling (factor = 0,79/year); % every 2 years is a good approach to keep the contact Rs below a certain limit. 3. Values 2010 to 2022 should stay in red Calculated values by using the scaling factor of 0.83

26 Jmax 2007 – significant changes
Impact of multi-core on interconnect length distributions was discussed regarding Jmax by Japan Design TWG, qualitatively as the first step. Assuming a symmetric multi-processor core, if the technology, the clock-frequency, and the number of logic stages per a pipeline is the same, the interconnect structures at the logic-gate level will be similar, leading to no-change in Jmax in the gate level interconnects. In addition, there might not be so much change in long wires, since repeaters are inserted either for single-core or multi-core, and so the load capacitances are similar. Based on the above discussion, there might not be so much impact of multi-core on interconnect Jmax. Numerical analysis will be done by Prof. Masu’s group with their model as the second step. : Critical points for the DC pulse current, where the minimum pitch and via-size are used for high density.

27 On-chip local clock (MHz) Intermediate half pitch (nm)
Jmax Change in Table 80 EM improvement technologies such as CuSiNx and Cu-alloy (CuAl etc.) have become manufacturable technologies. More than 20 times EM lifetime (T) improvements lead to about 5 times Jmax improvements assuming  T  J-2 Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 On-chip local clock (MHz) 4000 4191 4391 4600 4819 5049 5290 5542 Jmax (A/cm2) 2.08E+6 3.08E+6 3.88E+6 5.15E+6 6.18E+6 6.46E+6 8.08E+6 1.06E+7 0.91E+6 1.19E+6 1.38E+6 1.58E+6 1.70E+6 1.66E+6 1.90E+6 2.11E+6 Was Is Was Is 1.E+06 1.E+07 1.E+08 Jmax (A/cm2) Frequency (GHz) 3 4 5 6 7 8 1.E+05 Jmax (A/cm 2 ) <<<今回の山﨑の提案>>> 【白・黄・赤について】 ・5E6程度までは,CuSiN(In-situ Dielectric),Cu-AlloyでOKであり,量産技術のめどは立っているので白レンガ. ・1E7メタルキャップを想定しているので,チューニングで必要で黄レンガ. 【水色・白・ハッチについて】 ・ CuSiN(In-situ Dielectric)は2008年には解のひとつとして使われなければならないので,08年からPotential Solutionの白. ・メタルキャップは,同様に11年から使われるため,ここから白. ・いずれも使われ始める2年間は,白のQual/Pre-Proと定義してしまう.これをあらわすと次のページのようになる. 1.E+05 20 40 60 80 100 20 40 60 80 100 Intermediate half pitch (nm) Intermediate half pitch (nm)

28 Multi-core Impact on Interconnect
Wiring lengths change Critical path reduced (in core) Mechanical integrity challenges will change Jmax changes Hierarchical structure may no longer be necessary Converge to more fine pitch local/intermediate wires Power and ground delivered through grid Global delay challenge relaxed 3D may include multi-core Need to consider splitting metrics into: In-core (intra-tile) and Inter-core (inter-tile) New bandwidth requirements DPE DPE DPE DPE DPE DPE DPE DPE DPE DPE DPE DPE DPE DPE DPE DPE Main Processor Main Processor IO - Memory IF & Chip-to-Chip IF - Figure From ITRS 2006 Design TWG

29 Emerging Interconnect (1/2)
Use geometry 3D Air gap Use different signaling methods Signal design Signal coding techniques  Use innovative design and package options Interconnect - centric design Package intermediated interconnect  Chip-package co-design  Figure From Stanford The working group has quietly begun to address what is often referred to as beyond the roadmap, or after copper/low interconnect needs. This is referred to as emerging interconnect. Nearer term approaches with low risk is the use of air- gaps. 3D integration does not require the creation of a new material set, as optical interconnect does, but will be a complex and challenging system to implement.

30 Emerging interconnect (2/2)
Use different physics Optics (waveguides, emitters, detectors, free space, trans-impedance amps, modulators) RF/microwaves (transmitters, receivers, free space, waveguides) Terahertz photonics Radical solutions Nanowires/nanotubes/graphene Molecules Spintronics Quantum wave functions  One can use different propagation waves from microwave through near optical, all difficult. And of course it is always exciting to conceive of the role carbon nanotiubeso nano wire,, even self assembly. It is difficult to forecast inthis area but as the leading candidates from these areas are identified by a group led by Harodl Hosack of the SRC, initail roadmaps will be created. In the meantime, the introduction and rapid adoption of multi-c ore architecture for microprocessor has a big impact of the global delay challenge.

31 From low-k to no k - air gaps
Introduction of air gap architectures Creation of air gaps with non-conformal deposition Removal of sacrificial materials after multi-level interconnects Values of effective k-value down to 1.7 with low crosstalk levels Localized air gaps to maintain good thermal and mechanical properties Ultra-low k and Air gap (k<1.7) (CVD and Spin-on) Gaps in the dielctic, the nemesis of the dielctri cdepositoin engineerr in the in the aluminum ear are now being resurrected and featured as a soltiuon. We have to go back and find those bad process tools that came before HDP CVD. Seroulsyl, though, air gaps are a very realisticimprovement. Localized airgaps can also help by maiting good thermal conductivey and better mecahincl sternth theran a sub k=2 bulk deielctric

32 Hypothetical On-die Optical Interconnects with WDM
Wavelength specific modulator s1 s1 s2 s2 s3 s2 Waveguide s4 s4 s4 s5 s6 s6 Intel Technology Journal, Volume 8, Issue 2, 2004

33 High Density 3D Integration
Through silicon via (TSV) Reliability Physical metrics (pitch, diameter, density) Alignment tolerance Bond layer Interfacial defect density Adhesion List of “Difficult Challenges”, e.g. TSV processes, alignment, low k impact on TSV, etc.

34 High Density 3D Development Roadmap

35 2007 last words Metal 1 design rule concerns
Staggered contacted pitch used for definition 68 nm half pitch for 2007 High performance MPU pitches scaling at ~0.75/2 years until 2009 Returning to 0.7/3 years 2010 Convergence of MPU/ASIC and DRAM pitch in 2010 Commonality in the back-end (Cu based)

36 Summary of Notable 2007 changes
Low-k slowdown New range for bulk k and keff New Technology Introduction ALD barrier processes and metal capping layers for Cu are lagging in introduction. No solutions seen for Cu resistivity rise Power Metric Capacitance per unit length decreases due to decreases of the dielectric constant. The dynamic power is expected to increase because of the increased number of metallization layers, larger chip size and increased frequency.

37 Last words Must manage the power envelope More Moore More than Moore
Must continue to meet requirements of scaled metal/dielectric systems while developing CMOS-compatible equivalent scaling solutions Cu resistivity impact real but manageable materials solutions alone cannot deliver performance - end of traditional scaling More than Moore integrated system approach required Functional diversity enhances value Power is a problem, heat is a problem, performance variability is a problem, complexity is a problem There are many materials that are introduced from cobalt caps to enhanced reliability to ruthenium seeds for electrochemical deposition, but these materials do not solve3 global signal delay challenges. This is the end of traditional scaling – you may have heard the phrase equivalent scaling used. Here that means a more more integrated approach with design and packaging will deliver the expected performance.

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