1. Work in Progress --- Not for Publication 26 April 2001 1 Interconnect Working Group ITRS 2001 27 April 2001 Grenoble

2. Work in Progress --- Not for Publication 26 April 2001 2 Attendees Hans Barth - Europe Joaquin Torres - Europe Hyun Chul Sohn - Korea Ahihiko Ohsaki - Japan R Aoki - Japan C Case - US

3. Work in Progress --- Not for Publication 26 April 2001 3 Agenda Section updates: –Conductors –Dielectrics –Planarizaation –Etch –Reliability –System and performance –SOC

4. Work in Progress --- Not for Publication 26 April 2001 4 Agenda contd. Crosscut updates: –Modeling and simulations –Defect reduction –Metrology –ESH –Design

5. Work in Progress --- Not for Publication 26 April 2001 5 Nucleation/Conductors update Expanded description of ALD Spin etch planarization (CEP) (metal) Cu ECD combined with planarization Need for novel/potential cleans –Conductors, etch, dielectrics and planarization Reconciliation of new node info with wiring data

6. Work in Progress --- Not for Publication 26 April 2001 6 Wiring updates

7. Work in Progress --- Not for Publication 26 April 2001 7 Nucleation/Conductors update Expanded treatment of opto/electrical on chip materials needs –in System and Performance sections Add doped Cu conductors –unknown impact on resistivity vs dimension –allows higher current density, accommodates higher wire temp at local/inter levels Changed Cu resistivity for global wires (2.2 cm) New intermediate/local wiring Cu conductivity

8. Work in Progress --- Not for Publication 26 April 2001 8 Dielectrics update To address confusion on definition of effective k –add text that effective k includes all integration needs including cap, etch stops, hard masks Adding physical metrics on mechanical properties of porous materials from models so that text can support issues of using these weak materials options such as composites, fiber reinforcement included in text May add high k Tech Requirement k metric –material must meet temperature budget –still under consideration

9. Work in Progress --- Not for Publication 26 April 2001 9 Dielectrics update Add thermal properties –still under discussion Model effective k calculation that also includes crosstalk –with and without trench etch stop Photoresist poisoning of low k materials - text

10. Work in Progress --- Not for Publication 26 April 2001 10 Planarization update More detailed discussion of CEP Schematic and calculation for new dishing/erosion/thinning metrics Porous low k will require either alternative planarization or stopping layer/structural enhancements to be compatible with existing planarization techniques - text Addressing planarization of thick metal for inductors

11. Work in Progress --- Not for Publication 26 April 2001 11 Etch update New Potential Solutions figure –Distinguished by level and function –MRAM, FERAM –passives –De-emphasize HDP Etch is now driven by new materials and integration schemes Etch section - includes potential solutions with and without etch stops

12. Work in Progress --- Not for Publication 26 April 2001 12 System and Performance update Including resistivity increase (change) in performance calculations Agreement on current density - all regions agree 04/01 Include Raphael calculation and schematic for low k scenarios - for effective k and crosstalk Include in appendix some references on process variability effect on performance

13. Work in Progress --- Not for Publication 26 April 2001 13 SOC update Expanded detail on passives - create new technology requirements –thick metal thickness for inductors –Fe cores –Resistors –Capacitance per unit area metric - fF/micron 2 –Q factor

14. Work in Progress --- Not for Publication 26 April 2001 14 Cross Thrust ESH Chemicals, Materials and Equipment Management –add reuse and recycle for CMP and ECD –ULV chemical dispense Climate Change Mitigation –add PFC POU abatement Workplace Protection –address ClF 3, VOC from low k and POU abatement, PM schemes for hazardous chambers Resource Conservation –Alternative clean gases –Cu waste (CMP plus ECD) and water reclaim

15. Work in Progress --- Not for Publication 26 April 2001 15 Cross Thrust Metrology Dielectrics –porosity - size, distribution etc max pore diameter 10% of spacing average pore size 5% +- 3 sigma of spacing –k anisotropy - edge effects, - text Interfacial issues - contact to high k - text Conductors –voids - adding metric similar to dielectric but using metal half pitch –Cu ECD bath metrology - CVS, etc. Planarization –which of the new Technology Requirements need new metrology? –Cross section feature volume per unit length

16. Work in Progress --- Not for Publication 26 April 2001 16 Cross Thrust Metrology Etch –3DCD sidewall CD, possibly post planarization trench bottom profile –diagnostics for run to run stability –end point for low k (etch stops) –High A/R contacts (DRAM) - 3DCD endpoint for contact SoC –High k measurements - thickness, composition, k non-uniformity –R and L measurements - thick metal thickness

17. Work in Progress --- Not for Publication 26 April 2001 17 Cross Thrust Design Crosstalk metric - also Modeling Review the resistivity vs wiring level quandry - also modeling Capacitance per unit area metric - fF/micron 2 Q factor

18. Work in Progress --- Not for Publication 26 April 2001 18 Cross Thrust Modeling Crosstalk metric Review the resistivity vs wiring level quandry - also modeling Capacitance per unit area metric - fF/micron 2 Q factor

19. Work in Progress --- Not for Publication 26 April 2001 19 Cross Thrust PIDS Al on Cu for bonding pad Joe Adam had these problems Operating temp for harsh environments MEMS and interconnect Embedded epi in interconnect - possibly compound semi for emitter/receiver pairs

20. Work in Progress --- Not for Publication 26 April 2001 20 Cross Thrust Modeling Thermomechanical simulations issues request to modeling Thermal cycling in operation for multi-level structures Stress voiding Crosstalk at cell and higher effects, steadystate and operating

21. Work in Progress --- Not for Publication 26 April 2001 21 Difficult Challenges New materials Reliability Process integration Dimensional control Interconnect process with low/no device impact New materials and size effects Process complexity 3DCD Aspect ratios for fill and etch Solutions beyond copper and low Long termNear term

22. Work in Progress --- Not for Publication 26 April 2001 22 Remaining issues Adequate treatment of Cu resistivity impacts Need to agree on number of interconnect levels with respect to global wiring Proposed structural changes to potential solutions table