1. ITRS 2009 1 Metrology Roadmap 2010 EuropeAdrian Kiermasz (Metryx) Carlos Beitia (CEA LETI MINATEC) Philippe Maillot (ST) Delphine Le Cunff (ST) JapanYuichiro Yamazaki (Toshiba) Masahiko Ikeno (Hitachi High-Tech) KoreaTaiwan North AmericaYaw Obeng (NIST) George Orji (NIST) Jack Martinez (NIST) Dave Seiler (NIST) Ben Bunday (ISMI) Vic Vartanian (ISMI) Alain Diebold (CNSE – Univ. Albany)

2. ITRS 2009 2 Metrology Timing Model w/Technology Cycle Timing Source: 2009 ITRS - Executive Summary Fig 2b Months Development Production Volume (Wafers/Month) 2 20 200 2K 20K 200K Research -72 024 -48 -24-96 First Tech. Conf. Device Papers Up to ~12yrs Prior to Product 201920172015201320112021 1 st 2 Cos Reach Product First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product New for 2010 Process Research Tool Alpha Tool Beta Tool Product Tool Metrology/Char. Research Tool Metrology Alpha Tool Metrology Product Tool w/prec. & Uncert. Metrology Beta Tool w/precision

3. ITRS 2009 3 Metrology Materials and Test Structure Timing Model w/Technology Cycle Timing Source: 2009 ITRS - Executive Summary Fig 2b Months Development Production Volume (Wafers/Month) 2 20 200 2K 20K 200K Research -72 024 -48 -24-96 First Tech. Conf. Device Papers Up to ~12yrs Prior to Product 201920172015201320112021 1 st 2 Cos Reach Product First Tech. Conf. Circuits Papers Up to ~ 5yrs Prior to Product New for 2010 Metrology Research Tool Metrology Alpha Tool Metrology Product Tool w/prec. & Uncert. Metrology Research Samples Metrology Test Structure Samples @ Man. Design Rules Metrology Beta Tool w/precision

4. ITRS 2009 4 2010 Metrology Roadmap

5. ITRS 2009 5 Litho Metrology CD Metrology Extendibility Dual Patterning LER Litho Metrology for 3D Devices MuGFET MuCFET CD-SAXS Spacers Contour vs Design Muller Matrix Ellipsometry

6. ITRS 2009 6 Metrology for FEP Metrology for Generation II and III High K stacks EOT & Defects for Alternate Channel Materials Nano-topography & Local Stress measurements New Memory Materials Phase Change Memory FDSOI MuGFET MuCFET + III/V High µ Alternative Channel Matls Sidewall Metrology for 3D Devices

7. ITRS 2009 7 Metrology for ERM/ERD High carrier mobility and structural robustness have driven a considerable effort in Graphene research Measurement of Bi-layer misorientation Aberration corrected TEM How many Layers? Raman and LEEM Quantum Hall Effect observes the Berry Phase

8. ITRS 2009 8 Metrology for 3D Interconnect X-Ray Microscopy Overlay – IR Microscopy 1 4 3 F) Stress Metrology Raman Microscopy Bonding Defects - SAM

9. ITRS 2009 9 Metrology Summary FEP-Interconnect-Litho –PC and SST RAM - New materials for Metrology –Dual Patterning –3D Metrology – Confirm Geometry Requirements e.g. film thickness & properties on sidewall –Reference Methods for 3D –Composition & Stress – e.g. buried channels –EUV metrology requirements ERD-ERM –III-V & Ge Transition to FEP & PIDS –STT RAM Transition to FEP & PIDS Tunnel Dielectric Magnetic layers and interfaces –Redox RAM Local characterization of oxygen vacancies Real device dimensions and structures –Deterministic Doping Characterize dopants in 3D –Dopant vacancies and interstitials –Directed Self Assembly Defect detection Structure variations –Graphene Defects in CVD Graphene Mobility & Substrate Interactions Bandgap Measurement (Strain, etc.) 3D Metrology for Advanced Memory Graphene – C. Kisielowski