Presentation is loading. Please wait.

Presentation is loading. Please wait.

2005 ITRS Work in Progress – Do Not Publish 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Models For Public 12/13/05 Conference.

Similar presentations


Presentation on theme: "2005 ITRS Work in Progress – Do Not Publish 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Models For Public 12/13/05 Conference."— Presentation transcript:

1 2005 ITRS Work in Progress – Do Not Publish 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Models For Public 12/13/05 Conference Seoul, Korea (Rev 1, 12/12/05)

2 2005 ITRS Work in Progress – Do Not Publish 2 ORTC Overview ITRS Proposals Recommendation for one standard TWG table technology trend header –Presently continue to use DRAM stagger-contacted M1 as typical industry lithography driver – UNCHANGED from the 2003/2004 Roadmap Update –Remove ITRS single-product node label emphasis, to minimize industry guidance confusion; as we transition to product-oriented technology trend drivers and cycles* ORTC Table 1a,b - adjusted to Proposed Japan (STRJ) MPU/ASIC M1 Half- Pitch Trend –Stagger-contacted, same as DRAM –2.5-year Technology Cycle* (.5x/5yrs) –180nm/2000; 90nm/2005; 45nm/2010(equal DRAM) –Then continue on a 3-year Technology Cycle*, equal to DRAM ORTC Table 1a,b - added Proposed STRJ Flash Poly (Un-contacted dense lines) –2-year Technology Cycle* (0.5x/4yrs) –180nm/2000; 130nm/2002; 90nm/2004; 65nm/2006 –Then 3-year Technology Cycle* 1 year ahead of DRAM ORTC Table 1a,b – adjusted MPU/ASIC Printed Gate Length to FEP and Litho TWG agreement for ratio relationship to Final Physical Gate Length, which remains UNCHANGED from the 2005 ITRS targets (3-year cycle* after 2005) TWG table Product-specific technology trend driver header items to be added to individual TWG tables from ORTC Table 1a&b Chip Size Models connected to proposals and historical trends, incl. new Flash Model –Function Size [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)] –Functions/Chip [Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU] –Chip Size [hp MPU; cp MPU; DRAM; Flash] *Note: Cycle = time to 0.5x linear scaling every two cycle periods ~ 0.71x/ cycle

3 2005 ITRS Work in Progress – Do Not Publish 3 Source: 2003 ITRS - Exec. Summary Fig /2004 ITRS Definition of the Half Pitch - WAS [DRAM half-pitch determines the 2003 ITRS node] Metal Pitch Typical DRAM Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 Poly Pitch Typical MPU/ASIC Un-contacted Poly MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2 Typical MPU/ASIC Contacted Metal 1 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Metal 1 (M1) Pitch

4 2005 ITRS Work in Progress – Do Not Publish Definition of the Half Pitch – IS [No single-product node designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables] Metal Pitch Typical DRAM/MPU/ASIC Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Poly Pitch Typical flash Un-contacted Poly FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/ Lines

5 2005 ITRS Work in Progress – Do Not Publish 5 Production Ramp-up Model and Technology Node Volume (Parts/Month) 1K 10K 100K Months M 10M 100M Alpha Tool DevelopmentProduction Beta Tool Production Tool First Conf. Papers First Two Companies Reaching Production Volume (Wafers/Month) K 20K 200K Source: 2003 ITRS - Exec. Summary Fig 2 Fig 2 [UNCHANGED, except for node reference] IS: Cycle Timing

6 2005 ITRS Work in Progress – Do Not Publish 6 hp22hp32hp45hp65hp [Actual] Year of Production hp130 Technology Node (nm) WAS: 2003 ITRS Technology Nodes: 3-year cycle* 3-Year Technology Cycle 2-Year Technology Cycle [ actual] Note: Faster introduction of half-poly pitch from Flash is expected; and Doubling of transistors every 2 years from MPU/ASIC is expected. * Cycle Time = one-half of the time to reach a technology trend reduction to 0.5x Source: 2003 ITRS - Exec. Summary Past Future DRAM hpXX Node designation Was added in 2003 ITRS

7 2005 ITRS Work in Progress – Do Not Publish 7 Note: Faster introduction of half-poly pitch from Flash is expected; Doubling of transistors every 2 years from MPU/ASIC is expected 2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 1yr ahead of 3-Year Technology Cycle 2-Year Technology Cycle [98-06 ] Year of Production Technology - Uncontacted Poly H-P (nm) [Actual] [Actual] ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal Year of Production Technology - Contacted M1 H-P (nm) [July 08][July 02] [130]180[ 65] Year Technology Cycle 3-2-Yr Cycle] 3-Year Technology Cycle 14 IS: 2005 (05-20) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle 3-Year Technology Cycle 2-Year Technology Cycle [98-04] Year of Production Technology - Contacted M1 H-P (nm) [Actual] [Actual]

8 2005 ITRS Work in Progress – Do Not Publish 8 Figure 7& 8 ITRS Product Technology Trends Fig 7&8 Simplified – Option 1 MPU M1.71X/2.5YR Nanotechnology (<100nm) Era Begins GLpr IS = x GLph ITRS Range MPU & DRAM M1 & Flash Poly.71X/3YR Flash Poly.71X/2YR Gate Length.71X/3YR Before X/3YR After X/2YR

9 2005 ITRS Work in Progress – Do Not Publish 9 Note for Flash: SLC = Single-Level-Cell Size MLC = Multi-Level-Cell (Electrical Equivalent) Cell Size ITRS Range Figure xx ITRS Product Function Size (NEW) Fig xx Simplified 2 MLC bits/physical cell area) Flash: 4f 2 Last Design Physical Area Factor Improvement DRAM: 5f 2 Last Design Area Factor Improvement Logic Gate: NO Design Area Factor Improvement (Only Scaling) SRAM: Gradual Design Area Factor Improvement Flash: 2 bits/cell = 2f 2 Equivalent Area Factor)

10 2005 ITRS Work in Progress – Do Not Publish 10 Moores Law After 40 years (functions per chip) Pentium® Processor 486 DX Processor 386 Processor 286 Pentium® II Processor Pentium® III Processor Itanium® Processor Pentium® 4 Processor Itanium® 2 Processor 2X/2YR 2X/1YR 2X/2YR Source: Intel® Corp. Past Future

11 2005 ITRS Work in Progress – Do Not Publish 11 Chip Size Trends – 2005 ITRS Functions/Chip Model Proposal IS Past Future ITRS Range Average Industry Moores Law 2x Functions/chip Per 2 years Production, Affordable Chip Size**) ** Affordable Production Chip Size Targets: DRAM, Flash < 145mm 2 hp MPU < 310mm 2 cp MPU < 140mm 2 ** Example Chip Size Targets: 1.1Gt P07h intro in 2004/620mm prod in 2007/310mm 2 ** Example Chip Size Targets: 0.39Gt P07c intro in 2004/280mm prod in 2007/140mm 2 MPU ahead or = Moores Law 2x Xstors/chip Per 2 years Thru 2010

12 2005 ITRS Work in Progress – Do Not Publish ITRS Range Average Industry Moores Law 2x Functions/chip Per 2 years Figure yy ITRS Product Functions per Chip (NEW)

13 2005 ITRS Work in Progress – Do Not Publish 13 Past Future ITRS Range Chip Size Trends – 2003/04 vs.2005 ITRS DRAM & Flash (NEW) Model IS

14 2005 ITRS Work in Progress – Do Not Publish 14 Past Future ITRS Range Chip Size Trends – 2003/04 vs.2005 ITRS Flash (NEW) Model IS

15 2005 ITRS Work in Progress – Do Not Publish 15 Past Future ITRS Range Chip Size Trends – 2005 ITRS MPU Model Proposal IS

16 2005 ITRS Work in Progress – Do Not Publish 16 Summary DRAM Model stagger-contacted M1 is unchanged from 2003/2004 Update ITRS (single-Node reference removed) MPU Revised M1 to stagger-contact half-pitch (same as DRAM) and 2.5-year cycle* through 2010, then 3-year cycle* same as DRAM New Flash Model Added for un-contacted poly half-pitch and equal to DRAM contacted, but continues on 2-year cycle* to 1 year ahead of DRAM in 2006, then 3-year cycle* same as DRAM Printed MPU/ASIC Gate Length adjusted to new FEP and Litho TWGs ratio agreement, but Physical GL unchanged and on 3-year cycle* beginning 2005 Historical chip size models connected to new Product model proposals, including design factors, function size, and array efficiencies Average industry product Moores Law met or exceeded throughout ITRS timeframe [* ITRS Cycle definition = time to.5x linear scaling every two cycle periods]

17 2005 ITRS Work in Progress – Do Not Publish 17 Backup Note: ITRS Table Colorization Code Reference:

18 2005 ITRS Work in Progress – Do Not Publish 18 ORTC Table 1a,b (Near, Long Term) (Draft 04 review 10/31/05):

19 2005 ITRS Work in Progress – Do Not Publish 19 ORTC DRAM & Flash Prod Table 1c (Near Term) (Draft 04 review 10/31/05):

20 2005 ITRS Work in Progress – Do Not Publish 20 ORTC DRAM & Flash Prod Table 1d (Long Term) (Draft 04 review 10/31/05):

21 2005 ITRS Work in Progress – Do Not Publish 21 ORTC Table DRAM Intro 1e,f (Near, Long Term) (Draft 04 review 10/31/05):

22 2005 ITRS Work in Progress – Do Not Publish 22 ORTC MPU cp Table 1g (Near Term) (Draft 04 review 10/31/05):

23 2005 ITRS Work in Progress – Do Not Publish 23 ORTC MPU cp Table 1h (Long Term) (Draft 04 review 10/31/05):

24 2005 ITRS Work in Progress – Do Not Publish 24 ORTC MPU hp Table 1i (Near Term) (Draft 04 review 10/31/05):

25 2005 ITRS Work in Progress – Do Not Publish 25 ORTC MPU hp Table 1j (Long Term) (Draft 04 review 10/31/05):


Download ppt "2005 ITRS Work in Progress – Do Not Publish 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Models For Public 12/13/05 Conference."

Similar presentations


Ads by Google