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DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Metrology Roadmap 4 - 05 EuropeRien Stoup (PAN Analytical) Dick.

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Presentation on theme: "DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference Metrology Roadmap 4 - 05 EuropeRien Stoup (PAN Analytical) Dick."— Presentation transcript:

1 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Metrology Roadmap EuropeRien Stoup (PAN Analytical) Dick Verkley (FEI- Philips) Mauro Vasconi (ST) Mauro Vasconi (ST) JapanAtsuko Yamaguchi (Hitachi) KoreaChin Soobok (Samsung) Mann-Ho Cho (KRISS) Taiwan J.H. Sheih (TSMC) USJack Martinez (NIST) John Allgair (Freescale/SEMATECH) Steve Knight (NIST)* Alain Diebold (Int. SEMATECH)*

2 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference AGENDA 2005 ITRS Changes and Activities Lithography Metrology FEP Metrology Interconnect Metrology Key Challenges

3 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Transistor Evolution Today 90 nm Node Strain Enhanced Mobility Tomorrow New Materials CMOS pMOS FINFET Future 15 years Non-classical CMOS Beyond CMOS Molecular Switches ? Nanowire Transistor ?

4 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Nanotransistors – The Future Nano Transistors I dsat ~ W C ox (V G – V T ) sat Long Channel Behavior I dsat ( 1/Lg ) ( Carrier Mobility ) ( 1/EOT ) ? = C load V DD / I dsat C dependence A = Lg x W Dopant Conc. Short

5 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference New Business Established link with Emerging Research Materials group of ERD –ERM to report requirements –Metrology Reports Methods and Discussion –Provided update on aberration corrected TEM and 3D TEM developments Awaiting changes in Process Tolerance for Gate CD

6 2005 ITRS Changes

7 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Changes to Litho CD Metrology 45 nm contact Holes 16 nm Lines -176 nm Pitch ITRS July Presentation by Dan Wack – KLA-Tencor Scatterometry to at least the 45 nm Node Bryan Rice (Intel), SPIE, 2004 CD-SEM and Scatterometry can reach 32 nm Node w/improvement – impact of SOI not tested

8 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Experiments Simulation 2 m LWR increase becomes negligible at L=2 m Experiments & Simulation Confirmed by... 3 (nm) Inspection-area height L (nm) CD variation Average LWR Japan ITRS TWG Input LWR as a Function of L L above 2 Japan ITRS TWG Input LWR as a Function of L L above 2 m is really CD variation L value works for many resists as well as ADI, resist trim, and after etch L value works for many resists as well as ADI, resist trim, and after etch

9 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Wire width(nm) Resistivity(μΩcm) p=0(complete diffuse scattering) p=0.5 Measured Cu resistivity without Barrier Metal ρ(Al):2.74μΩcm p=0.3 Updated(May2004) Trend: Sidewall Control will become more Important Line Edge Roughness impacts Interconnect Resistance and Line Width Roughness impacts Transistor Leakage Current

10 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Measure LER and LWR = for reliability all spatial wavelengths between 1 micron to 20 nm taken over a 2 micron length with a spacing of 10 nm. LER: For monitoring Interconnect specular scattering – measure from 34 nm to twice the smallest interval using the smallest possible interval. Measure sidewall after barrier metal dep. LER and LWR reported as RMS values integrated over the frequency range specified below

11 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Overlay Metrology Issues are with the Overlay TargetsIssues are with the Overlay Targets Need better correlation between overlay target and device performanceNeed better correlation between overlay target and device performance –Current roadmap suggests that overlay is in good shape because precision for box – in – box targets meets ITRS guidelines –Step and Scan Litho Exposure tools contribute errors not measured by scribe line targets –Across die overlay issues are not captured by box –in – box target data analysis 2005 rewrite will capture these issues2005 rewrite will capture these issues

12 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference FEP Metrology: Increasing Emphasis on Areas beyond High k Increase in Mobility by using local stressing of transistors – Call for stress metrology by FEP Metal Gates increasingly important New transistor designs are already past R and into D. Example: FIN-FETs require metrology Strained SOI, GeOI considered longer term substrates Crystal Defect mapping including on patterned wafers metrology requirement for new substrates Mobility measurements are key

13 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Stress Measurement from transistor to wafer Wafer Bow Die Level Stress Transistor Level Stress Micro-Area Level Stress Nano-Raman and CBED Micro-Raman, XRD Die level flatness Laser Interferometry New Interferometry Method Laser Interferometry, New Interferometry

14 Trend : Use Modeling to connect what you can measure with what you need to know Example: Metrology of Strained Channel Devices MD Giles, et. al., VLSI Symposium 2004

15 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference 2005 Interconnect Activities Porous low k is being overshadowed by the need to lower k value of barrier layer and etch stops for 45/32 nm node. Long term solution for interconnect is ambiguous.

16 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference New Comments on Interconnect Metrology 3D CD especially Sidewall Roughness for trench/via are critical needs In Process Development, LER is an important figure of merit for sidewall and AFM can give sidewall/via roughness vs depth as well as trench CD and profiles which provide important control for etch processes Need metrology for thickness and uniformity for hard mask above low after CMP – how is erosion pattern dependent

17 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference ERD and ERM Premise: Aberration corrected TEM/STEM needed for nano-electronics Latest TEM and STEM results show improved imaging for sub 0.1 nm beams. We have not reached the limit where improving beam diameter does not improve imaging Nanowires and nanotubes serve as ideal systems to test theoretical and experimental understanding of beam propagation and image formation. - reduced stresses and amorphous films on the surface

18 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Concept Proven : Aberration Correction BeforeAfter STEM – Batson, Dellby, and Krivanek, Nature 418, 617 (2002) Si(110) HR-TEM – Jai, Lentzen, and Urban, Microsc. Microanal. 10, 174, SrTiO 3

19 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Conclusions CD Measurement improvements show a path to the 32 nm Node Propose definition for LWR and including LER Transistor channel engineering requires Stress and Mobility Measurement Interconnect requires Sidewall Measurements for barrier/seed and low trench

20 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Acknowledgements David Bell and his 2003 M&M paper on nanowire TEM Christian Kiselowski Dave Muller Steve Pennycook Suzanne Stemmer

21 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Change in Transistor Behavior

22 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Why measure CD for NanoTransistors = C load V DD / I dsat 1. CD impacts Capacitance C A = Lg x W Dopant Conc. 2. CD impacts Threshold Voltage Likharev has shown that below 10 nm CD, Threshold Voltage is very sensitive to CD At CD = 5 nm Process range is 0.2 nm ~ 1 atom

23 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Red moves back in? for Litho Metrology Technology Requirements

24 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference 2005 Potential Solution Assessments Conflicting Reports on high keV CD- SEM Damage Impact of Metal Gate on CD-SEM and Scatterometry – Metal Dependent Impact of Gate thickness on CD Measurement for end of roadmap New Method identified as potential solution – CD-SAXS (NIST Wen-li Wu)

25 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference FEP : Non-Classical CMOS Metrology

26 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference FEP Metrology Questions FINFET Metrology needs? –Doping –corner rounding makes FIN fully depleted with thicker FIN –Gate Dielectric Thickness –Timing schedule is ?? 2005 –FIB cross-section accuracy issues. Particles on 450 mm wafer 1mm edge exclusion Local Strain High k Gate stack (EOT, k, thickness) SOI/BOX Gate workfunction

27 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference High Volume ICs use CMOS w/ Locally Strained Si Strained Si substrates not used PMOS Compressive Strain increased hole mobility 45 nm NMOS Tensile Stress SiN Layer increased electron mobility From T. Ghani, et. al., IEDM 2003, p 978. Courtesy Intel

28 DRAFT – Work In Progress - NOT FOR PUBLICATION April 2005 – ITRS Public Conference Gaps in Interconnect Metrology VOID Detection in Copper vias & lines now based on 1/10 via diameter Quality of Barrier/Seed on sidewalls Killer Pore Detection in Low Non destructive metrology for adhesion and (eff) (at operating freq.) for patterned wafers


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