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2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design ITWG ITRS-2003 December 2, 2003 Taiwan Japan: Ichiro Yamamoto, Tamotsu Hiwatashi Taiwan:

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Presentation on theme: "2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design ITWG ITRS-2003 December 2, 2003 Taiwan Japan: Ichiro Yamamoto, Tamotsu Hiwatashi Taiwan:"— Presentation transcript:

1 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design ITWG ITRS-2003 December 2, 2003 Taiwan Japan: Ichiro Yamamoto, Tamotsu Hiwatashi Taiwan: Chung-Ping Chen USA: Andrew Kahng (Europe: Ralf Brederlow)

2 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design ITWG Contributions to ITRS System Drivers Chapter –Defines IC products that drive manufacturing and design technologies –ORTCs + System Drivers = framework for technology requirements –SoC-centric organization, with three fabrics Processor Mixed-Signal Memory Design Chapter –Cross-cutting challenges: (1) productivity, (2) power, (3) design for manufacturing, (4) interference, (5) error-tolerance –Design cost and productivity models –Technology areas: (1) design process, (2) system-level design, (3) logical/physical/circuit design, (4) design verification, (5) design test ORTC support –Frequency, Power, Density models

3 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Big Picture Message: Cost of Design threatens continuation of the semiconductor roadmap –Design cost model –Challenges are now Crises : software, verification, analog, cost... Strengthen bridge from semiconductors to applications, software, architectures –Hertz and bits are not the same as efficiency and utility –System Drivers chapter, with productivity and power foci Strengthen bridges among ITRS technologies –Shared red bricks can be solved (or, worked-around) more cost-effectively variability, leakage, low-k, … –Manufacturing Integration cross-cutting challenge –Living ITRS framework to promote consistency validation

4 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan SYSTEM DRIVERS CHAPTER

5 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan 2001 System Drivers Chapter Outline ScopeScope –High-volume custom (MPU, memory), AMS, SOC –Market Drivers MPUMPU Mixed-SignalMixed-Signal SoCSoC –Multi-Technology –High-Performance –Low-Cost, Low-Power –Trends (Power and Design Productivity, based on LP-PDA model) Market Drivers SoC scope and taxonomy –Multi-Technology, High- Performance, Cost-Driven SoC trends –LP-PDA and Power –Cost and SiP integration Component Fabrics –MPU –Mixed-Signal –Memory

6 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan System Drivers Chapter Changes Rewriting and reorganization SOC-centric structure –Key challenges: productivity, power, heterogeneous integration, test SOC LP PDA model –Table of Performance and die size, Device and memory composition –Battery technology –Mixed-signal content SOC LP Device Table reconciliation Embedded memory section Planned for : SOC impact of cost drivers –SIP Multi-Technology integration alternatives –Low metal/mask count Embedded DSP, MCU Off-chip signaling bandwidth

7 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan SoC Taxonomy Component Fabrics: Processor, Memory, Mixed-Signal

8 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Reqd Performance for Multi-Media Processing GOPS Video AudioVoice CommunicationRecognition Graphics FAX Modem 2D Graphics 3D Graphics MPEG Dolby-AC3 JPEG MPEG1 Extraction MPEG2 Extraction MP/ML MP/HL Compression VoIP Modem Word Recognition Sentence Translation GOPS: Giga Operations Per Second 100 Voice Auto Translation 10Mpps 100Mpps MPEG4 Face Recognition Voice Print Recognition SW Defined Radio Moving Picture Recognition

9 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan ITRS SoC Low-Power PDA Model Study Reference Design: personal digital assistant (PDA) Composed of CPU, DSP, peripheral I/O, and memory

10 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Example SoC for PDA 0.18um / 400MHz / 470mW (typical) CPU I-cache 32KB D-cache 32KB I2C FICP USB MMC UARTAC97 I2S OST GPIO SSP PWMRTC DMA controller LCD Cnt. MEM Cnt. PWR CPG SDRAM 64MB Flash 32MB LCD Peripheral Area 4 – 48MHz Data Transfer Area 100MHz Processor Area Max 400MHz MM Application MP3 JPEG Simple Moving Picture 6.5MTrs. Available Time 6-10Hr Specification USB MMC KEY Sound

11 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan PDA Model Characteristics

12 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan LSTP Power Dissipation

13 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan LOP Power Dissipation

14 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Power-Constrained Chip Composition Memory Logic

15 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Technology Needs (e.g., Design) Multi-everything optimization –Mix of HP, LOP, LSTP devices in same core –Design tools must simultaneously optimize use of Vdd, Vt, Tox knobs as well as device sizing Body bias control, Lgate bias, … Dynamic voltage, frequency scaling Clock gating Sleep modes Operating system and application control Other technology area needs: PIDS, A&P, Test…

16 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Analog / Mixed-Signal Update Adapted to analog & RF technologies for wireless communications working group within PIDS –System Drivers Chapter text aligned with the new PIDS subchapter Drivers and Figures of Merit –ADC:stays as predicted –LNA: stronger performance improvement than expected in 2001 –VCO: FoM is adjusted to technology (some changes in text) Numbers remain relatively similar Benefits from certain technology measures as expected, but VCO improvement versus technology remains weak part of RF circuits –PA: stays as predicted Less CMOS-centric; some enhancements occur when looking at SiP

17 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Embedded Memory SRAM, Flash, DRAM technology parameters – Cell size, additional masks, area efficiency – Access time, power active/standby, refresh, lifetime, SEU Figure of Merit for memory: – 1/ (cell size * area efficiency * mask-count factor * effective power (static or dynamic) * access time (R or RW)) Define Drivers and their needs – Granularity and hierarchy – Volatile/non-volatile storage – Code (size) vs. data (size voice, image, …) – Bandwidth vs. storage trade-off – Error correction codes, testability, yield

18 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan DESIGN CHAPTER

19 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design Chapter Changes Canonical design flow context, design system architecture and design process Design cost model refinement Standalone analog CAD, circuits, SOI content Soft-error (including logic) Rewriting and reorganization Interactions with other ITWGs –Ground rules (poly half-pitch, contacted M1 pitch, …) impact on layout density –Benefits of, and lower bounds for, technology improvements (dielectric permittivity, CD variability, …) –Off-chip signaling roadmap –High-performance (MPU) system power requirements

20 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design Process Merged Design Process and Methodology Precepts Challenges organized around 5 Key Trends –Tight Coupling –Design for Manufacture –Increasing Level of Abstraction –Increasing Level of Automation –Early Verification New Figure to show evolution and trends –Based on STRJ-WG1 Canonical Flow –Different methodologies or applications would have variant flows –Show implied evolution of design system architecture New Table to summarize challenges and strategies

21 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Canonical Design Flow (STRJ-WG1) Provides context for detailed technology discussions Also serves as grounding for design cost analysis Required Design Technology innovations –RTL synthesis = synthesis technology that creates RT-level models from architecture models –HW/SW co-synthesis = synthesis technology that creates architecture models from behavior models I.e., outputs architecture models for HW and source codes for SW

22 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan

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24 Revised ITRS Design Cost Model Description of model –Rewritten to further clarify model, data, and conclusions –Introduced footnotes to explain geographical issues –Remains as Appendix in 2003 Design Chapter Model itself –Introduced cost model tree to capture key components –Included software design in tree –Accomodates canonical design flows Data –Performed substantial sanity checks successful overall –Future versions will emphasize software, large-block reuse –Calibration across regions (salary, productivity data) due to market differences should be resolved in future versions

25 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan

26 Productivity Evolution

27 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan CAD for Analog / Mixed-Signal / RF To close the productivity gap, must focus on: Description languages (analog and digital, electrical and non-electrical) System performance evaluation and design-space exploration Circuit synthesis and sizing Schematic validation Design for manufacturing Analog/RF layout synthesis Interconnect and substrate extraction, modeling, simulation Power Analog IP and reuse Top-down and bottom-up methodologies

28 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Expected Breakthroughs in AMS CAD 2002/032004/052006/07 Specification, validationMixed-signal description languages Multi-language support; full system simulation Complete specification-driven design flow Architectural designAlgorithm-oriented design Language-based performance evaluation Synthesizable AMS description Mixed A/D and RF physical design Procedural layout generation Design centering, performance estimation Constraint-driven synthesis; behavior to layout Parasitic extraction, modeling, simulation EMI simulation2D / 3D modeling; order reduction (lines and fields) Fault-tolerant circuit architectures; robustness Test preparationAMS fault simulation BIST for AMS circuits Generally accepted fault models for all design levels ATPG

29 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan SUMMARY

30 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Summary System Drivers Chapter –New material Embedded memory –Improvements to existing material SOC-centric chapter reorganization SOC Low-Power PDA driver model MPU, Mixed-Signal discussions Design Chapter –New material Analog section Canonical design flow context –Improvements to existing material Design cost model Design process and design system architecture

31 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan THANK YOU !

32 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan 2003 ITRS Low-Power PDA Model (R. Saleh, K. Uchiyama, I. Yamamoto) Goals –Validate existing models and modify results based on any new data –Modify ITRS System Drivers text accordingly

33 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan 2003 ITRS Low-Power PDA Model (R. Saleh, K. Uchiyama, I. Yamamoto) Goals –Validate existing models and modify results based on any new data –Modify ITRS System Drivers text accordingly Outcomes –Keep power-related projections –Remove productivity-related projections –Table 1: Reduction of GOPS values, inclusion of battery technology advances decided to stay with original version –Gate leakage, mixed-signal content, eSRAM-eDRAM transition point also left unchanged Many refinements, but conclusions do not change

34 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan

35 Summary System Drivers Chapter –New material Embedded memory –Improvements to existing material SOC-centric chapter reorganization SOC Low-Power PDA driver model MPU, Mixed-Signal discussions Design Chapter –New material Analog section Canonical design flow context –Improvements to existing material Design cost model Design process and design system architecture

36 2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan 2003 ITRS Low-Power PDA Model Goals –Validate existing models and modify results based on any new data –Modify ITRS System Drivers text accordingly Outcomes –Keep power-related projections –Remove productivity-related projections –Reduction of GOPS values, inclusion of battery technology advances decided to stay with original version –Gate leakage, mixed-signal content, eSRAM-eDRAM transition point also left unchanged Many refinements, but conclusions do not change


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