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Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 1 Design TWG 2004-2005 Goals 1. Development of design color.

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Presentation on theme: "Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 1 Design TWG 2004-2005 Goals 1. Development of design color."— Presentation transcript:

1 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 1 Design TWG Goals 1. Development of design color tables - Design technology requirements - Design technology solutions 2. Revision of tables and content - Addition of DFM (Technology Access) section - Cost/ROI model improvement - e-RAM content consistency and model accuracy - New DSP/MCU content - Further SIP content and alignment with SoC - Reorganize AMS + modeling/simulation 3. Application / product alignment - Alignment with product (NEMI) roadmap (with other TWGs)

2 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 2 Design TWG Strategy Goal2004 Work2005 WorkChapter 1. Develop color tables - Extended general requirements - Preliminary general solutions Development of detailed color tables - requirement (quantit.) - solutions (qualit.) Design 2. Revise tables and content - Revise e-RAM model - Better SIP content - SoC cost model - Preliminary DFM section - Preliminary DSP/MCU - Embed AMS & modeling - Complete DFM ("Technology Access) section (DFM, CD control, libraries,…) - Total cost/ROI model - Complete DSP/MCU Design 3. Align with applications - Align existing requirements to PDA model - Identify mapping products- ITRS drivers - Complete set of ITRS drivers on an SoC application basis System drivers

3 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 3 Back Up Slides

4 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 4 1. Design Color Table Development Current requirements / solutions tables by –General –Design process –System level –Logic, circuit, and physical design –Verification –Test Size ~ 50 requirements, 50 solutions

5 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 5 1. Design Color Table Development Feedback summary (Japan) –Agree on definitions of productivity and power –Consistency / links with ORTC –Decomposition of requirements –Number of requirements and target audience –Alternative break-downs (by design objectives, by fabrics) Feedback summary (Europe) –Clearly define each parameter e.g. (1 sentence in e-RAM section –Choose driver (fabrics, app., objective) Include that as comment to table rows or make extra row –Cost/area as requirement

6 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 6 1. Design Requirements Color Tables RequirementCommentsSRCLeader Complexity (system) Xtors/chipCombine from ORTC/appORTC..Smith SoC Productivity - design cycle (mo) Improvement %, By application Include re-spins? G.Smith Carballo %SW in overall productivity - design cycle (mo) Improvement Include SW % by application G.Smith Carballo Productivity - Logic Mtx per designer-year improvement %Smith Carballo Power efficiency - dynamic power reduction beyond scaling Definition, Precond, assumption needed PIDS Table value ÷ Target value PIDS+Brederlo w + Jap Power efficiency - standby power reduction beyond scaling (X) PIDS+Brederlo w + Jap Area density – increase beyond scaling (X) PIDS+Brederlo w Manufacturing interface - %cov.Put in Test tableKahng Design cost (improvement, norm)Smith General requirements

7 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 7 1. Design Requirements Color Tables RequirementCommentsReqSRCLeader # of verifiable statesGrowingProductivity % states covered (non-f)Growing?Productivity # of diverse fabrics modeled simultaneusly (eDRAM, etc.) Yield/Cost Productivity # of factors to optimize at once Area, Speed, Power, Test t,Y Productivity # of tools under single APIEg. Sim(A+D)+FV Eg. P&R+STA Productivity Manageable power densityClarifyPower Analyzable noise frequencyClarify? % cross-chip variabilityYield/cost % manufacturability improvement Yield/cost Design process requirements

8 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 8 1. Design Requirements Color Tables RequirementCommentsInfo sourceLeader Analog scalability (versus digital?) Clarify % design block reuse # of technologies implemented (eDRAM, eFPGA, SiGe, optical, MEMS) Clarify System-level design requirements

9 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 9 1. Design Requirements Color Tables RequirementCommentsInfo sourceLeader FOM for incremental analysisDefine i. analysis FOM for interconnect planningDefine i.planning % asynchronous global signalingClarify % Tolerable Defect density % parameter uncertaintyClarify matching/% AC/DC power reduction > scalingRepeated before MTTF contribution (reliability)Define contribution # simult. analysis objectivesArea, Power, etc. # of circuit families supportedImportant? % analog content synthesized % design on predictable platforms % adaptive/self-repairing circuits Logic / circuit / physical design requirements

10 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Requirements Color Tables RequirementCommentsInfo sourceLeader Verifiable design size (gates) % logic formally verified % coverage for largest design % effort in SW verification % reuse of verification code % acceptable cost increase % verification time variability % concurrency Average granularity of block % design formally verified % analog formally verified # of technologies simult. verified (MEMS, EO or EB devices, etc.) Verification requirements

11 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Requirements Color Tables RequirementCommentsInfo sourceLeader Max. at-speed test frequency Max. serial I/Os test frequency % chip self-tested % logic with BIST % AMS with BIST % yield improvement through test % block test reused in SoC # technologies tested on same chip (MEMS, EO, etc.) % defects detected by burn-in test P, SDFT and fault tolerant design for logic soft errors % chip self-reconfigurable Test requirements

12 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Solutions Color Tables RequirementCommentsInfo sourceLeader High-freq. full chip noise analysis Concurrent multi-factor optimization Automated package analysis Integrated A/D flows Parallel processing-aware flows Variability across entire flow Automated mask correction Automated SW+HW synthesis Design process solutions

13 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Solutions Color Tables RequirementCommentsInfo sourceLeader System-level component reuse Automated interface synthesis Explicit system-level energy- performance trade-off Multi-fabric implementation planning (AMS, RF, MEMS…) SW-SW co-design and verification On-chip network design methods System-level design solutions

14 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Solutions Color Tables RequirementCommentsInfo sourceLeader Fully incremental analysis Synthesis and timing accounting for variability (statistical?) Circuit/layout enhancement accounting for variability Macro/chip leakage analysis Power management analysis & logic insertion SOI SoC tools Analog synthesis (circuit/layout) Cost-driven implementation flow Implementation tools for sensors Non-static logic implementation Platform-specific tools Logic, circuit and physical design solutions

15 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Solutions Color Tables RequirementCommentsInfo sourceLeader Semi-formal verification Problem difficulty characterization Bug coverage determination CAD support for D-f-Verifiability Hierarchical verification algorits. Predictable verification time with known cost penalty MPU-specific verification Concurrent multi-core processor verification A/D/multi-fabric automated co- verification Design verification solutions

16 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Solutions Color Tables RequirementCommentsInfo sourceLeader DFT, test, measurement…for I/O DFT for low-cost ATE Power management during test DFT for Signal integrity DFT, BIST for core-based SOC e-memory B-I-S-diagnosis+repair AMS DFT/BIST SOC/SIP test with MEMS/EO On-chip multi-GHz RF circuit test Design for burn-in defect screens DFT for logic soft errors System-level on-line test Timing-related noise fault models Design test solutions

17 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design SIP content, SoC alignment SIP –alignment and data issues SoC –How to align with SIP, migration

18 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design "Technology Access" Section Content –DFM –Libraries –Cost –CD variability survey? Possible leads –Andrew Kahng (driver) –J. Mainard & S. Nassif (IBM) - unconfirmed

19 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Possible Section Structure Key New position/section Needed? Libraries/models DFM Cost Simple enumeration of challenges

20 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Embedding of Content AMS –Elimination of separate AMS section –Incremental immersion of AMS content in document –Possible lead Peter Modeling/simulation –Embed lone paragraph withing rest of document –Add to list of cross-cutting challenges

21 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish Design Cost/ROI model Agreement on definition of cost Additions of non-cost metrics –What metrics ROI? –How to get data –Possible leaders Smith, Carballo

22 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers DSP/MCU content From F to logic-sensible length scale (e.g., contacted M1). –Will impact SRAM A-factor model and logic density model SRAM model –Recalibrate to the last few years of data (Dennis, Andrew) Add more design innovation –Would increase chip white-space unless more overhead or –increase growth rate of SRAM and logic transistor counts – look at spreadsheet Key questions –Is multi-core model (2X SRAM+logic per node) still OK? –Calibration data (e.g. 140mm 2, 310mm 2 still correct?) –Date of deployment and model implications of eDRAM –Redoing the MPU model = server-desktop vs. mobile

23 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers e-RAM model e-memory dynamic power roadmap –2010 discontinuity –Review dynamic power calculation model (all memories) e-memory static power roadmap –System Drivers value <> PIDS table+model value –Review leakage power calculation model –Impact of Vt variations? FRAM –Widely used embedded, already integrated in SoC –Derive FRAM roadmap (like SRAM, FLASH, e-DRAM) MRAM? Flash –Andrew digging info on NOR-Flash

24 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers e-RAM model e-memory dynamic power roadmap –2010 discontinuity problem was spreadsheet mistake –Review dynamic power calculation model (all memories) e-memory static power roadmap –System Drivers value <> PIDS table+model value –Review leakage power calculation model –Impact of Vt variations? FRAM –Widely used embedded, already integrated in SoC –Derive FRAM roadmap (like SRAM, FLASH, e-DRAM) MRAM? Flash –Andrew digging info on NOR-Flash

25 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers e-RAM model/content Consistency Accuracy Content –DRAM –SRAM –Flash

26 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers Product Alignment (NEMI) Will improve alignment with other documents –With systems chapter, based on each systems driver –With NEMI emulators, based on each NEMI emulator Issues –Design organized by challenges and traditional EDA fields –Systems drivers based on fabric/platform –NEMI emulators based on product, NEMI is US organization Actions (tentative) –Talk with NEMI about geographical composition –Aggressively improve each sections alignment with s. drivers –Improve understanding of NEMI-ITRS drivers connection –Possible lead Andrew

27 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 27 Drivers SoC/SIP HP MT? LC-LP MPUDSP AMS eMemory GamingPDANPWireless Architecture Applications (NEMI) Fabrics (ITRS)MEMS BioChip Futures 8. System Drivers Product Alignment (NEMI) Current

28 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers Product Alignment (NEMI?) Drivers MPUDSP AMS eMemory GamingPDANPWireless Architectures Applications (NEMI?) Fabrics (ITRS)MEMS BioChip Futures Current High performanceLow power A1A1 A2A2 A3A3 A4A4 α1α1 β1β1 γ1γ1 δ1δ1

29 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers Product Alignment (NEMI?) Year Parameter A1A1 A2A2 A3A3 A4A4

30 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers Product Alignment (NEMI) Example product –System Drivers Reference Design –Personal digital assistant (PDA) Composition –CPU –DSP –Peripheral I/O –Memory 0.18um / 400MHz / 470mW (typical) CPU I-cache 32KB D-cache 32KB I2C FICP USB MMC UARTAC97 I2S OST GPIO SSP PWMRTC DMA controller LCD Cnt. MEM Cnt. PWR CPG SDRAM 64MB Flash 32MB LCD Peripheral 4 – 48MHz Data Transfer 100MHz Processor Max 400MHz 6.5MTrs. USB MMC KEY Sound

31 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish System Drivers Product Alignment (NEMI) SoC challengesMPU challengesAMS challenges Productivity improvement Power management System-level integration Test methodology Design/verification productivity Power management/delivery Input/output bandwidth Multi-core organization Parametric yield Skills and productivity Decreasing supply Increasing analog content Higher speed Crosstalk Parametric variations

32 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 32 Interaction With Other TWGs ( PIDS, PIDS/Litho/FEP, Test, Assembly/Packaging, Yield ) TWGNeeded infoTWGContact 1. Development of color tablesWhat %perf/power growth is design? 0 Are color tables OK? Tolerable defect density PIDS Test Yield 2. Further SIP content and alignment with SoC Provide # & speed I/Os, max. power per application? Assembly/ packaging Test 3. Addition of "Technology Access" From PIDS Dev. param. variability generate high-level DTWG data (also (1.)) Tolerable defect density. Design rules. PIDS/ Litho/ FEP Yield 4. Embedding of AMS and modeling/simulation Difficult to doModeling/ simulation Peter + Ralf

33 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 33 Interaction With Other TWGs ( PIDS, PIDS/Litho/FEP, Test, Assembly/Packaging, Yield ) TWGNeeded infoTWG Collab/co ntact 5. Cost/ROI model improvement System Drivers What part is design V. manuf V. test V. packaging? (PDA) PIDS+ test + factory i. + Alan 6. Improved DSP/MCU contentWhat part of 70% growth is design? 0 ORTC PIDS 7. e-RAM content consistency and model accuracy Vt variation, I gate, Flash data, bits/cell, ECC Provide #IPs per chip Read detailed table and say if its useful PIDS Test 8. Alignment with product roadmap (NEMI?) Align Systems Drivers to PIDS too Align by apps/drivers? SoC/SoP migration data SoC/SoP yield model PIDS Assembly/P Yield

34 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 34 Back-up Slides

35 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 35 Discussion on Cost Versus ROI Should we gather ROI trends? Appendix Material

36 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 36 Cost Versus ROE/ROI Investor care about ROE Assets Debt Equity A = D + E Revenue Cost/expense Interest/tax Net profit ROE /..

37 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 37 ROI versus Cost Return On Investment a crucial metric –Cost is not the only variable! ROI = - I + R t - C t (1 + r) t t = 1 n Investment (upfront cost) CostRevenue Required return (risk) Time (years)

38 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 38 DT Investment versus Overall costs 2X EDA investment could half total design cost… –…if it achieves 7% more productivity growth 2X EDA investment ½ total cost

39 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 39 ROI Example SoC

40 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 40 Cost versus ROI Impact of Time/productivity TTM increases ROI, as it reduces time parameter 1. Higher revenues 2. Earlier revenues 3. Similar cost!

41 Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san 2004 Work in Progress – Do Not Publish 41 Cost versus ROI Impact of Uncertainty/Risk Uncertainty lowers ROI, as it increases perceived risk


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