Presentation on theme: "ITRS Design ITWG 2008 1 Design and System Drivers Worldwide Design ITWG Key messages: 1.- Software is now part of semiconductor technology roadmap 2.-"— Presentation transcript:
ITRS Design ITWG Design and System Drivers Worldwide Design ITWG Key messages: 1.- Software is now part of semiconductor technology roadmap 2.- Design technology has become key to technology control 3.- Design pacing unabated despite manufacturing slowdown 4.- MtM will bring a new set of Design requirements/solutions (09)
ITRS Design ITWG Overview (2004-8) 1. Increasingly quantitative roadmap 2. Increasingly complete driver set Explore Design metrics Design Technology metrics Revised Design metrics Revised Design Technology Metrics Consumer Portable Driver Consumer stationary Portable Drivers Consumer Stationary, Portable, Networking Drivers More Than Moore analysis + iNEMI Driver study System Drivers Chapter Design Chapter 2008 Revised Design Metrics DFM extension Updated Consumer Stationary, Portable, and Networking Drivers More Than Moore extension + iNEMI + SW !!
ITRS Design ITWG System Level Design & SOFTWARE Hardware design productivity is growing appropriately –Requirements correspond roughly with solutions –Innovations pacing properly (transistors / designer / year) Large gap in software productivity possibly opening up –If hardware accelerators are heavily leveraged, problem mitigated –Otherwise, possibly 100X gap can affect memory size, other Adding new parameters to requirements/solutions tables –Hardware design productivity - requirement –Software design productivity - requirement –Software design productivity (assuming only software implementation) –System design productivity innovations – solutions (Fig. 1 in chapter) (alternative Scenario)
ITRS Design ITWG Impact of Design on Sigma (Variability) Manufacturing Device Circuit Logic / function System / SW Use variability model Goal Quantify how many sigmas can design reduce Approach Inventory of design techniques / tools Match inventory to parameters or correlations in model Use variability model to capture delta in sigmas Inputs (manufacturing) Check overall variation
ITRS Design ITWG Technology Pacing (Design) Impact of 3 year shift on Design –Largely insignificant – number of functions basically unchanged –Possible impact on selected requirements (e.g., DFM) Updated Design requirements (DFM) (% variability model, etc.) PIDS / FEP / Litho 3-year shift
ITRS Design ITWG More Than Moore (Design) More than Moore brings new set of requirements/solutions –Will create additional inventory of parameters Existing requirementsExisting solutions Additional requirementsAdditional solutions E.g. –System-level (packaging) –Circuit (inter-chip parasitics modeling/simulation) –Layout (SiP global layout) –DFM (package-chip, SiP DFM) Existing Additional
ITRS Design ITWG Design and System Drivers Worldwide Design ITWG Key messages: 1.- Key system drivers constantly updated (2008, 2009,…) 2.- Design pacing unabated despite manufacturing slowdown 3.- MtM will bring a new set of System Drivers parameters (09) 4.- Will continue to broaden System Drivers based on markets 5.- Frequency-power trade-off will continue its adjustment 6.- Design/SD ITWG deeply engaged in cross-TWG initiatives
ITRS Design ITWG Overview (2004-8) 1. Increasingly quantitative roadmap 2. Increasingly complete driver set Explore Design metrics Design Technology metrics Revised Design metrics Revised Design Technology Metrics Consumer Portable Driver Consumer Stationary, Portable Drivers Consumer Stationary, Portable, Networking Drivers More Than Moore analysis + iNEMI Driver study System Drivers Chapter Design Chapter 2008 Revised Design Metrics DFM extension Updated Consumer Stationary, Portable, and Networking Drivers More Than Moore extension + iNEMI + SW !!
ITRS Design ITWG Key System Drivers Constantly Updated Consumer Driver Model 2008: Updated power model with realistic dynamic power –Memory dynamic power 10X less than modeled previously Will identify key driver requirements, explore coloring –E.g., excessive power beyond portable limit (1 W) Will explore RF/A/MS for future portable consumer drivers –Extends existing driver (or, future wireless driver is possible) Also ongoing: additional parameters per Test requests –Upon provision of rationale/definition: Clocks, I/Os, currents, etc. 8 W max total (2022) 4.3 W max total (2022)
ITRS Design ITWG Design Pacing Unabated Despite Manufacturing Slowdown Impact of 3-year shift on System Drivers –2008: MPU frequency model intact –2008: Consumer driver model power updates to reflect 3-year GL shift –2009: Incorporate impact of FINAL parameters from 3-year shift Updated Consumer portable (power) Updated MPU model (power) PIDS / FEP / Litho 3-year shift
ITRS Design ITWG More Than Moore Brings Alternative Set of Parameters ( ) Will create additional inventory of parameters System Drivers Consumer portable (SoC)Consumer portable (SiP) Power Normalized Cost System Drivers Consumer stationary (SoC)Consumer stationary (SiP) Performance Normalized Cost CONCEPT: Current SoC scenariovs. Additional SiP scenario
ITRS Design ITWG Frequency-Power Trade-Off Will Continue and Extend Current priorities Power #1 goal Frequency slowdown Multi-core enables trade-off Need to track trade-off Market vigilance Yearly adjustment Possible 2009 survey
ITRS Design ITWG (defense) Network Consumer Portable Office Medical Automotive Consumer stationary MPU PE(DSP) AMS Memory Fabrics Markets ? (FPGA) New System Drivers? Not So Fast… New FPGA driver suspended (until resource identified) Others (defense) eliminated to synchronize with latest iNEMI Others might be assessed in 2009 (medical, automotive)
ITRS Design ITWG System Drivers and iNEMI (2009) Proposal to iNEMI: iNEMI develops Portable System Arch. Template Need commitment including designer resource Application processor Baseband processor Memory NAND Flash Memory Wireless Flash Audio / video codec Power mgt. I/O controller I/O transceivers Other (MEMS, etc.) Processing POWER Memory / Flash COST Analog / I/O NOISE SENSITIVITY
ITRS Design ITWG Design & Key ITRS Cross-TWG Initiatives With Interconnect (A&P): 3D / TSV roadmapping survey With PIDS, FEP, IRC: Modeling and requirements support for CV/I RO-based transistor metric With CSTNSG: Updated frequency, SRAM area, active area (yield) projects With More Than Moore Study Group: Definition of SIP-scenario System Driver roadmaps to complement existing SOC-scenario Driver roadmaps