Presentation is loading. Please wait.

Presentation is loading. Please wait.

ITRS Design ITWG 2010 1 ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes.

Similar presentations


Presentation on theme: "ITRS Design ITWG 2010 1 ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes."— Presentation transcript:

1 ITRS Design ITWG ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma

2 ITRS Design ITWG Roadmap Work in Progress – Do Not Publish! Explore Design metrics Design Technology metrics Revised Design metrics Revised Design Technology Metrics Consumer Portable Driver Consumer Stationary, Portable Drivers Consumer Stationary, Portable, Networking Drivers More Than Moore (MTM) analysis + iNEMI Driver study System Drivers Chapter Design Chapter 2008 Revised Design Metrics DFM extension Updated Consumer Stationary, Portable, and Networking Drivers MTM extension + iNEMI + SW !! 2009 Additional Design Metrics DFM Extension System level extension Updated Consumer Stationary, Portable architecture, and Networking Drivers MTM extension + iNEMI synch + SW !! Overview (2004-Today) 1. Increasingly quantitative roadmap 2. Increasingly complete driver set MTM RF+AMS Driver Updated Consumer, MPU, and Networking Drivers Power roadmap chart Upgraded RF+AMS section 2010

3 ITRS Design ITWG Selected Messages Design productivity continues to be center focus of design technology roadmap, as scaling depends on time to market Accurate design productivity and cost models are key 2.Power consumption has become the key technical parameter that controls feasible semiconductor scaling Power-driven device roadmap, frequency pushed to flat trend 3.More Than Moore has become a necessary component of semiconductor product scaling Mixed SiP-SoC analog-digital drivers need to be roadmapped

4 ITRS Design ITWG Design / System Drivers 2010 * * Plans 1.Design chapter Improvement of design productivity and cost models * Develop Power Chart based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * 2.System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * 3.Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2 nd EDA Roadmap Workshop *

5 ITRS Design ITWG Design / System Drivers 2010 * * Plans 1.Design chapter Improvement of design productivity and cost models * Develop Power Chart based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * 2.System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * 3.Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2 nd EDA Roadmap Workshop *

6 ITRS Design ITWG ITRS Design Productivity Roadmap Model for upcoming Power Management Roadmap 6 IC Implementation Tool Set RTL Functional Verif. Tool Suite Transaction Level Modeling Very large block reuse AMP Parallel Processing Intelligent Testbench Many Core Devel. ToolsSMP Parallel Processing Executable Specification Transactional Memory System Design Automation Source: ITRS

7 ITRS Design ITWG ITRS Design Productivity Roadmap Model for upcoming Power Management Roadmap 7 IC Implementation Tool Set RTL Functional Verif. Tool Suite Transaction Level Modeling Very large block reuse AMP Parallel Processing Intelligent Testbench Many Core Devel. ToolsSMP Parallel Processing Executable Specification Transactional Memory System Design Automation Source: ITRS Design Productivity INNOVATIONS Design Cost

8 ITRS Design ITWG ITRS Design Productivity Roadmap Expected upcoming Power Management Roadmap 8 IC Implementation Tool Set RTL Functional Verif. Tool Suite Transaction Level Modeling Very large block reuse AMP Parallel Processing Intelligent Testbench Many Core Devel. ToolsSMP Parallel Processing Executable Specification Transactional Memory System Design Automation Source: ITRS Design for Power INNOVATIONS Power Efficiency

9 ITRS Design ITWG SOC Modeling by Japan STRJ-WG1

10 ITRS Design ITWG Design / System Drivers 2010 * * Plans 1.Design chapter Improvement of design productivity and cost models * Develop Power Chart based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * 2.System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * 3.Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2 nd EDA Roadmap Workshop *

11 ITRS Design ITWG Roadmap Work in Progress – Do Not Publish! 11 Design and System Drivers ITRS-iNEMI Domain Space Chip levelSystem level Tech requirements Market requirements iNEMI (emulators) ITRS (Drivers) *Source: ITRS Design/System Drivers TWG Chairman, Dr. Juan-Antonio Carballo

12 ITRS Design ITWG A&D Network Consumer Portable Office Medical Automotive Consumer Stationary MPU PE/DSP AMS Memory Fabrics Markets ? SIP New System Drivers? At the right pace… Is SIP a new fabric ? What application is the right driver for (leading edge) 3D/TSVs ? 2010? ?

13 ITRS Design ITWG ITRS-iNEMI Domain Space SiP-SoC More-than-Moore Proposal Chip levelSystem level Tech requirements Market requirements Portable emulator RF/AMS Driver Portable consumer driver 123 Update portable driver Update portable emulator PA Case Study (SoC v. SiP)

14 ITRS Design ITWG h An Alternative Driver Tuner / Demodulator Inclusion of AMS/RF sub-driver from ITRS AMS driver Equivalent cost = NRE + non-NRE per- board cost 14 Power (SiP) Power (SoC) Equivalent cost (SoC) Equivalent cost (SiP) Tuner-demod case Study RequirementDescription TunerResolution, operating freqs, power ADC/DAC#bits, order, power, etc. Demodulator /FEC decoder Gain-bandwidth, power Additional rows for combined analog-digital model

15 ITRS Design ITWG SOC Modeling by Japan STRJ-WG1

16 ITRS Design ITWG Power-Constrained Frequency Scaling Intrinsic frequency scaling + activity scaling 13% per year Still exceed 150W in : –To meet market needs frequency growth limited 8% per year 2010 (expected): –To meet market needs / additional constraints: flat YTY trend 8% frequency scaling Power < 150W

17 ITRS Design ITWG Cross-TWG Interaction: Design-PIDS Device speed scaling: HiPerf CV/I improves by 13%/year –Use headroom for further power savings? Three devices in the ITRS roadmap –High Performance (HP): Highest Ion and Ioff, lowest CV/I –Low Operating Power (LOP): Lowest VDD, medium Ion, Ioff and CV/I –Low Standby Power (LSTP): Lowest leakage, low Ion, high CV/I Design providing guidance as to targeted ratio of device characteristics –Preferred order of dynamic power: LOP < LSTP << HP –Preferred order of leakage power: LSTP < LOP << HP Ratio of HP : LOP : LSTP R1 R2 R3 Parameters Target design freq.(GHz) Device CV/I Device Ioff INPUT FEEDBACK Application drivenTechnology driven Design GroupPIDS Group

18 ITRS Design ITWG Design / System Drivers 2010 * * Plans 1.Design chapter Improvement of design productivity and cost models * Develop Power Chart based on STRJ & productivity chart * Ensure 3D / TSV content consistent with other chapters * Improve DFM section, including Design for reliability rows * Overhaul of Verification *, L/C/P sections * 2.System Drivers chapter Update MPU frequency roadmap (flat trend), evaluate impact * Update of SOC-CP and SOC-CS models (driven from TWGs) * Update AMS/RF Driver / fabric with Wireless TWG * More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * 3.Other Cross-TWG and public activity PIDS: increase design-driven requirements definition * 3D/TSV: hold for ACTION * Continue other key interactions: A&P, Interconnect, Test * Incorporate input from 2 nd EDA Roadmap Workshop *

19 ITRS Design ITWG h ITRS-iNEMI MTM SOC/SIP Design/Integration Update of ITRS and iNEMI Portable Drivers Inclusion of AMS/RF sub-driver from ITRS AMS driver Equivalent cost = NRE + non-NRE per-board cost 19 Other AMS PA (RF) Power (SiP) Power (SoC) Equivalent cost (SoC) Equivalent cost (SiP) PA Case Study

20 ITRS Design ITWG Gaps in EDA (IEEE DAC Roadmap Workshop Technology EDA nature Metrics

21 ITRS Design ITWG Selected Messages Design productivity continues to be center focus of design technology roadmap, as scaling depends on time to market Accurate design productivity and cost models are key 2.Power consumption has become the key technical parameter that controls feasible semiconductor scaling Power-driven device roadmap, frequency pushed to flat trend 3.More Than Moore has become a necessary component of semiconductor product scaling Mixed SiP-SoC analog-digital drivers need to be roadmapped


Download ppt "ITRS Design ITWG 2010 1 ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes."

Similar presentations


Ads by Google