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Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 15 Memory Circuits.

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Presentation on theme: "Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 15 Memory Circuits."— Presentation transcript:

1 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 15 Memory Circuits

2 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 15.1 (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point(s) of the latch.

3 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

4 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 15.3 (a) The set/reset (SR) flip-flop and (b) its truth table.

5 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

6 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

7 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

8 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 15.7 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips.

9 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 15.8 A block diagram representation of the D flip-flop.

10 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure 15.9 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase non-overlapping clock whose waveforms are shown in (b).

11 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) A master–slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required.

12 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A 2 M+N -bit memory chip organized as an array of 2 M rows × 2 N columns.

13 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A CMOS SRAM memory cell.

14 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

15 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The normalized value of V Q versus the ratio (W/L) 5 /(W/L) 1 for the circuit in Fig This graph can be used to determine the maximum value permitted for (W/L) 5 /(W/L) 1 so that is V Q kept below a desired level.

16 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure Voltage waveforms at various nodes in the SRAM cell during a read-1 operation.

17 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

18 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

19 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The one-transistor dynamic RAM (DRAM) cell.

20 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure When the voltage of the selected word line is raised, the transistor conducts, thus connecting the storage capacitor C S to the bit-line capacitance C B.

21 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

22 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

23 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure An arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left.

24 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

25 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The active-loaded MOS differential amplifier as a sense amplifier.

26 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address.

27 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer.

28 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A tree column decoder. Note that the colored path shows the transistors that are conducting when A 0 = 1, A 1 = 0, and A 2 = 1, the address that results in connecting B 5 to the data line.

29 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/6 tP.

30 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) A one-shot or monostable circuit. Utilizing a delay circuit with a delay T and an XOR gate, this circuit provides an output pulse of width T. (b) The delay circuit can be implemented as the cascade of N inverters where N is even, in which case T = N tP.

31 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure A simple MOS ROM organized as 8 words ×4 bits.

32 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.

33 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

34 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure The floating-gate transistor during programming.

35 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. Figure P15.11


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