Presentation on theme: "S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of."— Presentation transcript:
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07 Dynamic logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate Dynamic circuit operation is divided into two modes: precharge and evaluate
S. Reda EN160 SP’07 What if the input is ON during precharge? What if pulldown network is ON during precharge? –Contention arises because both pMOS and nMOS will be ON Use series evaluation transistor to prevent fight.
S. Reda EN160 SP’07 Logic effort for dynamic circuits Very fast with very low logical effort
S. Reda EN160 SP’07 Dynamic circuits have a problem: Monotonicity requirement Dynamic gates require monotonically rising inputs during evaluation –0 → 0 –0 → 1 –1 → 1 –But not 1 → 0
S. Reda EN160 SP’07 Implications of Monotonicity But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!
S. Reda EN160 SP’07 Domino Logic Follow dynamic stage with inverting static gate –Dynamic / static pair is called domino gate –Produces monotonic outputs
S. Reda EN160 SP’07 Domino optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic 8-input multiplexer built from two 4-input dynamic multiplexers
S. Reda EN160 SP’07 Dual-Rail Domino Domino only performs noninverting functions: –AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem –Takes true and complementary inputs –Produces true and complementary outputs sig_hsig_lMeaning 00Precharged 01‘0’ 10‘1’ 11invalid
S. Reda EN160 SP’07 Leakage problems Dynamic node floats high during evaluation –Transistors are leaky (I OFF 0) –Dynamic value will leak away over time –Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node –Must be weak enough not to fight evaluation
S. Reda EN160 SP’07 Charge sharing Dynamic gates suffer from charge sharing Solution: add secondary precharge transistors Typically need to precharge every other node Big load capacitance C Y helps as well
S. Reda EN160 SP’07 Domino Summary Domino logic is attractive for high-speed circuits –1.5 – 2x faster than static CMOS –But many challenges: Monotonicity, leakage, charge sharing, noise, and high dynamic power Widely used in high-performance microprocessors Static CMOS Ratioed Circuits Cascode Voltage Switch Logic Pass-transistor Circuits Dynamic Circuits Circuit Families