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**Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory**

Manoel E. de Lima David Harris Harvey Mudd College

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**Outline Introduction MOS Capacitor nMOS I-V Characteristics**

pMOS I-V Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models 3: CMOS Transistor Theory

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**Introduction So far, we have treated transistors as ideal switches**

An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C (DV/Dt) -> Dt = (C/I) DV Capacitance and current determine speed Also explore what a “degraded level” really means 3: CMOS Transistor Theory

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**MOS Capacitor Gate and body form MOS capacitor Operating modes**

Accumulation Depletion Inversion 3: CMOS Transistor Theory

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**Terminal Voltages Mode of operation depends on Vg, Vd, Vs**

Vgs = Vg – Vs Vgd = Vg – Vd Vds = Vd – Vs = Vgd - Vgs Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence Vds 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation 3: CMOS Transistor Theory

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nMOS Cutoff No channel Ids = 0 Vgs ≤ 0 3: CMOS Transistor Theory

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**nMOS Linear Channel forms Current flows from d to s e- from s to d**

Ids increases with Vds Similar to linear resistor 3: CMOS Transistor Theory

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**I-V Characteristics In Linear region, Ids depends on**

How much charge is in the channel? How fast is the charge moving? 3: CMOS Transistor Theory

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Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel 3: CMOS Transistor Theory

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Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Qchannel = CV C = Cg = eoxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt Cox = eox / tox 3: CMOS Transistor Theory

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**Carrier velocity Charge is carried by e-**

Carrier velocity v proportional to lateral E-field between source and drain v = 3: CMOS Transistor Theory

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**Carrier velocity Charge is carried by e-**

Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = 3: CMOS Transistor Theory

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**Carrier velocity Charge is carried by e-**

Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: t = 3: CMOS Transistor Theory

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**Carrier velocity Charge is carried by e-**

Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: t = L / v 3: CMOS Transistor Theory

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**nMOS Linear I-V = β (Vgs-Vt )Vds -Vds2/2 = β (Vgs-Vt )Vds Now we know**

How much charge Qchannel is in the channel How much time t each carrier takes to cross Cox= oxide capacitance = β (Vgs-Vt )Vds -Vds2/2 = β (Vgs-Vt )Vds It is a region called linear region. Here Ids varies linearly, with Vgs and Vds when the quadratic term Vds2/2 is very small. Vds << Vgs-Vt 3: CMOS Transistor Theory

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**nMOS Saturation Channel pinches off Ids independent of Vds**

We say current saturates Similar to current source 3: CMOS Transistor Theory

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**nMOS Saturation I-V = β (Vgs-Vt )Vds -Vds2/2 Ids = β (Vgs-Vt ) 2/2**

If Vgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current = β (Vgs-Vt )Vds -Vds2/2 Where 0 < Vgs – Vt <Vds, considering (Vgs-Vt )=Vds we have Ids = β (Vgs-Vt ) 2/2 3: CMOS Transistor Theory

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nMOS I-V Summary nMOS Characteristics 3: CMOS Transistor Theory

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**Example We will be using a 0.6 mm process for your project**

From AMI Semiconductor tox = 100 Å m = 350 cm2/V*s Vt = 0.7 V Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 l 3: CMOS Transistor Theory

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**pMOS I-V All dopings and voltages are inverted for pMOS**

Mobility mp is determined by holes Typically 2-3x lower than that of electrons mn 120 cm2/V*s in AMI 0.6 mm process Thus pMOS must be wider to provide same current In this class, assume mn / mp = 2 3: CMOS Transistor Theory

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Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion 3: CMOS Transistor Theory

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**Gate Capacitance Approximate channel as connected to source**

Cgs = eoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm 3: CMOS Transistor Theory

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**Diffusion Capacitance**

Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Varies with process 3: CMOS Transistor Theory

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**Pass Transistors We have assumed source is grounded**

What if source > 0? e.g. pass transistor passing VDD 3: CMOS Transistor Theory

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**Pass Transistors We have assumed source is grounded**

What if source > 0? e.g. pass transistor passing VDD Vg = VDD If Vs > VDD-Vt, Vgs < Vt Hence transistor would turn itself off nMOS pass transistors pull no higher than VDD-Vtn Called a degraded “1” Approach degraded value slowly (low Ids) pMOS pass transistors pull no lower than Vtp 3: CMOS Transistor Theory

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Pass Transistor 3: CMOS Transistor Theory

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Pass Transistor Ckts 3: CMOS Transistor Theory

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**Effective Resistance Shockley models have limited value**

Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace Ids(Vds, Vgs) with effective resistance R Ids = Vds/R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay 3: CMOS Transistor Theory

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**RC Delay Model Use equivalent circuits for MOS transistors**

Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width 3: CMOS Transistor Theory

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**RC Values Capacitance C = Cg = Cs = Cd = 2 fF/mm of gate width**

Values similar across many processes Resistance R 6 KW*mm in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 l) Or maybe 1 mm wide device Doesn’t matter as long as you are consistent 3: CMOS Transistor Theory

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**Inverter Delay Estimate**

Estimate the delay of a fanout-of-1 inverter R in pMOS is divided by 2 since its width is the double of the nMOS 3: CMOS Transistor Theory

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**Inverter Delay Estimate**

Estimate the delay of a fanout-of-1 inverter 3: CMOS Transistor Theory

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**Inverter Delay Estimate**

Estimate the delay of a fanout-of-1 inverter 3: CMOS Transistor Theory

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**Inverter Delay Estimate**

Estimate the delay of a fanout-of-1 inverter d = 6RC 3: CMOS Transistor Theory

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**X +5V +5V R Ioh Iih Voh(min) Vih(min) GND GND Transistor não conduz**

Out Vil=0 X Transistor não conduz Roff 1010 Voh(min) Vih(min) GND GND Tempo (seg) Tensão(V) Vih(min) Nível ´1´ Capacitor

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**+5V +5V R Iol Iil Vol(max) Vil(max) GND GND Transistor conduz Vil(max)**

In Iol Iil Out Vih=´1´ Vol(max) Vil(max) Transistor conduz Ron 1 K GND GND Tempo (seg) Tensão(V) Vil(max) Nível ´0´ Capacitor inicialmente carregado = “1”

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