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1 COMP541 Transistors and all that… a brief overview Montek Singh Sep 8, 2014.

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Presentation on theme: "1 COMP541 Transistors and all that… a brief overview Montek Singh Sep 8, 2014."— Presentation transcript:

1 1 COMP541 Transistors and all that… a brief overview Montek Singh Sep 8, 2014

2 Transistors as switches  At an abstract level, transistors are merely switches 3-ported voltage-controlled switch 3-ported voltage-controlled switch  n-type: conduct when control input is 1  p-type: conduct when control input is 0 2

3 Silicon as a semiconductor  Transistors are built from silicon  Pure Si itself does not conduct well  Impurities are added to make it conducting As provides free electrons  n-type As provides free electrons  n-type B provides free “holes”  p-type B provides free “holes”  p-type Figure 1.26 Silicon lattice and dopant atoms

4 MOS Transistors  MOS = Metal-oxide semiconductor  3 terminals gate: the voltage here controls whether current flows gate: the voltage here controls whether current flows source and drain: are what the current flows between source and drain: are what the current flows between Figure 1.29 nMOS and pMOS transistors

5 nMOS Transistors  Gate = 0 OFF = disconnect OFF = disconnect  no current flows between source & drain  Gate = 1 ON= connect ON= connect  current can flow between source & drain  positive gate voltage draws in electrons to form a channel Figure 1.30 nMOS transistor operation

6 pMOS Transistors  Just the opposite Gate = 1  disconnect Gate = 1  disconnect Gate = 0  connect Gate = 0  connect  Summary: 6

7 CMOS Topologies  There is actually more to it than connect/disconnect nMOS: pass good 0’s, but bad 1’s nMOS: pass good 0’s, but bad 1’s  so connect source to GND pMOS: pass good 1’s, but bad 0’s pMOS: pass good 1’s, but bad 0’s  so connect source to V DD  Typically use them in complementary fashion: nMOS network at bottom nMOS network at bottom  pulls output value down to 0 pMOS network at top pMOS network at top  pulls output value up to 1 only one of the two networks must conduct at a time! only one of the two networks must conduct at a time!  or smoke may be produced if neither network conducts  output will be floating if neither network conducts  output will be floating 7

8 Inverter 8 AP1N1Y 0ONOFF1 1 ON0

9 NAND 9 ABP1P2N1N2Y 00ON OFF 1 01ONOFF ON1 10OFFON OFF1 11 ON 0

10 3-input NOR Gate? 10

11 2-input AND Gate? 11

12 Transmission Gates  Transmission gate is a switch: nMOS pass 1’s poorly nMOS pass 1’s poorly pMOS pass 0’s poorly pMOS pass 0’s poorly Transmission gate is a better switch Transmission gate is a better switch  passes both 0 and 1 well When EN = 1, the switch is ON: When EN = 1, the switch is ON:  A is connected to B When EN = 0, the switch is OFF: When EN = 0, the switch is OFF:  A is not connected to B  IMPORTANT: Transmission gates are not drivers will NOT remove input noise to produce clean(er) output will NOT remove input noise to produce clean(er) output simply connect A and B together (current could even flow backward!) simply connect A and B together (current could even flow backward!) use very carefully! use very carefully!

13 Logic using Transmission Gates  Typically combine two (or more) transmission gates Together form an actual logic gate whose output is always driven 0 or 1 Together form an actual logic gate whose output is always driven 0 or 1  Exactly one transmission gate drives the output; all remaining transmission gates float their outputs  Example: XOR when C = 0, TG0 conducts when C = 0, TG0 conducts  F = A when C = 1, TG1 conducts when C = 1, TG1 conducts  F = A’ therefore: therefore:  F = A xor C 13 TG0 TG1

14 Tristate buffer and tristate inverter  When enabled: sends input to output  When disabled: output is floating (‘Z’)  Implementation: Tristate buffer using only a pass gate Tristate buffer using only a pass gate  If on: output  input  If off: output is floating Tristate inverter Tristate inverter  Top half and bottom half are not fully complementary  Either both conduct: output  NOT(input) –will act as a driver!  Or both off: output is floating 14

15 Power Consumption  Power = Energy consumed per unit time Dynamic power consumption Dynamic power consumption Static power consumption Static power consumption

16 Dynamic Power Consumption  Energy consumed due to switching activity: All wires and transistor gates have capacitance All wires and transistor gates have capacitance Energy required to charge a capacitance, C, to V DD is CV DD 2 Energy required to charge a capacitance, C, to V DD is CV DD 2 Circuit running at frequency f: transistors switch (from 1 to 0 or vice versa) at that frequency Circuit running at frequency f: transistors switch (from 1 to 0 or vice versa) at that frequency Capacitor is charged f/2 times per second (discharging from 1 to 0 is free) Capacitor is charged f/2 times per second (discharging from 1 to 0 is free) P dynamic = ½CV DD 2 f P dynamic = ½CV DD 2 f

17 Static Power Consumption  Power consumed when no gates are switching Caused by the quiescent supply current, I DD (also called the leakage current) Caused by the quiescent supply current, I DD (also called the leakage current) P static = I DD V DD P static = I DD V DD

18 Power Consumption Example  Estimate the power consumption of a wireless handheld computer V DD = 1.2 V V DD = 1.2 V C = 20 nF C = 20 nF f = 1 GHz f = 1 GHz I DD = 20 mA I DD = 20 mA P = ½CV DD 2 f + I DD V DD = ½(20 nF)(1.2 V) 2 (1 GHz) + = ½(20 nF)(1.2 V) 2 (1 GHz) + (20 mA)(1.2 V) (20 mA)(1.2 V) = 14.4 W = 14.4 W


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