CMOS Digital Integrated Circuits 1 Lec 7 CMOS Inverters: Dynamic Analysis and Design.
Published byModified over 4 years ago
Presentation on theme: "CMOS Digital Integrated Circuits 1 Lec 7 CMOS Inverters: Dynamic Analysis and Design."— Presentation transcript:
CMOS Digital Integrated Circuits 1 Lec 7 CMOS Inverters: Dynamic Analysis and Design
CMOS Digital Integrated Circuits 2 CMOS Inverters – Dynamic Analysis and Design n Goals Understand the detail dynamic analysis of the CMOS inverter. Understand one set of design form CMOS equations. Understand the basic CMOS design process using the CMOS static and CMOS design form dynamic equations.
CMOS Digital Integrated Circuits 3 CMOS Dynamic Analysis Capacitance Model for CMOS V out V DD V in C gs,p C int C sb,p C gs,n C gd,n C gd,p C sb,n C db,p C db,n CgCg FO
CMOS Digital Integrated Circuits 4 CMOS Dynamic Analysis Capacitance Model for CMOS The aggregate capacitance driven by the output node of a CMOS inverter is in detail working from left to right, C load = C input + C int + C g in which C input = C gd,n + C gd,p + C db,n + C db,p (intrinsic component) C int = interconnect capacitance C g = thin-oxide capacitance over the gate area (extrinsic component)
CMOS Digital Integrated Circuits 5 CMOS Dynamic Analysis Delay-Time Definitions V OH V 50% V OL V in t idealized step input V OH V 50% V OL V out t t0t0 t1t1 t2t2 t3t3 V 90% V 10% t tAtA tBtB tCtC tDtD V 50 % = V OL +(V OH -V OL )/2. = (V OH +V OL )/2 τ PHL = t 1 -t 0 τ PLH = t 3 -t 2 τ P = (τ PHL +τ PLH )/2 V 10% = V OL +0.1(V OH -V OL ) V 90% = V OL +0.9(V OH -V OL ) τ fall = t B -t A τ rise = t C -t D
CMOS Digital Integrated Circuits 6 CMOS Dynamic Analysis Delay-Time Calculation (First Order Estimates) The simplest approach of calculating the propagation delay is based on estimating the average capacitance current during charge down/up. where
CMOS Digital Integrated Circuits 7 CMOS Dynamic Analysis Delay-Time Calculation (More Accurate)(1/4) The propagation delay can be found more accurately by solving the state equation of the output node. The current flowing through C load is a function V out as τ PHL : PMOS is off. The equivalent circuit during high-to-low output transition is V in nMOS i D,n C load V out V in V out iCiC i D,p i D,n
CMOS Digital Integrated Circuits 8 CMOS Dynamic Analysis Delay-Time Calculation (2/4) The nMOS operates in two regions, saturation and linear, during the interval of τ PHL. Saturation Region i D,n =(k n /2)(V in -V T,n ) 2 =(k n /2)(V OH -V T,n ) 2 »Plug i D,n into C load dV out /dt=-i D,n, and integrate both sides, we get t 1 ’ -t 0 = 2C load V T,n /[k n (V OH -V T,n ) 2 ] V OH =V DD V 50% V OH -V T,n V out t t0t0 t1t1 nMOS in saturation nMOS in linear region t1’t1’
CMOS Digital Integrated Circuits 9 CMOS Dynamic Analysis Delay-Time Calculation (3/4) Linear Region i D,n = (k n /2)[2(V in -V T,n )V out -V out 2 ] = (k n /2)[2(V OH -V T,n )V out -V out 2 ] »Plug i D,n into C load dV out /dt=-i D,n, and integrate both sides, we have Finally, since V OH =V DD and V OL =0, we have V OH V 50% V OH -V T,n V out t t0t0 t1t1 nMOS in saturation nMOS in linear region t1’t1’
CMOS Digital Integrated Circuits 10 CMOS Dynamic Analysis Delay-Time Calculation (4/4) τ PLH : NMOS is off. The equivalent circuit during low-to-high output transition is With the similar way (t 0 →t 1 ’ →t 1 ∕0→|V T,p |→V 50% ∕linear →saturation), we can have V in pMOS i D,p C load V out V DD
CMOS Digital Integrated Circuits 11 CMOS Inverter Design n Design for Performance Keep capacitance small Increase transistor size »Watch out for self-loading! Increase V DD (????)
CMOS Digital Integrated Circuits 12 CMOS Inverter Design Delay as a Function of V DD V DD increases → τ PHL /τ PLH decreases. However, the power consumption also increases. 0.818.104.22.168.822.22.4 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V DD (V) τ pHL (normalized)
CMOS Digital Integrated Circuits 13 CMOS Inverter Design Device Sizing (1/5) 2468101214 2. 0 2.2 2.4 2.6 2.8 3.2 3.4 3.6 3.8 x 10 -11 S τ p (sec) 3.0 Self-loading effect: Intrinsic capacitances dominate (for fixed load)
CMOS Digital Integrated Circuits 14 CMOS Inverter Design Device Sizing (2/5) n NMOS/PMOS Ratio R = W p / W n 11.522.533.544.55 3 3.5 4 4.5 5 x 10 -11 R pp (sec) PLH PHL PP
CMOS Digital Integrated Circuits 15 CMOS Inverter Design Device Sizing (3/5) Self-Loading Effect C load = C gd,n (W n ) + C gd,p (W p ) + C db,n (W n ) + C db,p (W p ) + C int +C g = f(W n,W p ) Using the junction capacitance expressions in Chapter 3, we have C db,n = (W n D drain +x j D drain )C j0,n K eq,n +(W n +2D drain )C jsw,n K eq,n C dp,n = (W p D drain +x j D drain )C j0,p K eq,p +(Wp+2D drain )C jsw,p K eq,p Therefore, C load can be rewritten as C load = α 0 + α n W n + α p W p where 0 = D drain (2C jsw,n K eq,n +2C jsw,p K eq,p +x j C j0,n K eq,n +x j C j0,p K eq,p )+C int +C g n = K eq,n (C j0,n D drain +C jsw,n ) p = K eq,p (C j0,p D drain +C jsw,p )
CMOS Digital Integrated Circuits 16 CMOS Inverter Design Device Sizing (4/5) Therefore, τ PHL and τ PLH are The ratio between the channel widths W n and W p is usually dictated by other design constraints such as noise margins and the logic inversion threshold. Let’s this transistor aspect ratio be defined as R ≡ W p /W n. Then, the propagation delay can be represented as
CMOS Digital Integrated Circuits 17 CMOS Inverter Design Device Sizing (5/5) As we continue increase the values of W n and W p, the propagation delay will asymptotically approach a limit value for lager W n and W p, The propagation delay times cannot be reduced beyond the above limits, and the limit is independent of the extrinsic capacitances.
CMOS Digital Integrated Circuits 18 CMOS Inverter Design Impact of Rise Time on Delay τ p H L ( n s e c ) 0.35 0.3 0.25 0.2 0.15 τ rise (nsec) 10.80.60.40.20 Propagation delay increases since both PMOS and NMOS are on during the charge-up and charge- down events.
CMOS Digital Integrated Circuits 19 CMOS Inverter Design Impact of Channel Velocity Saturation n The drain current is linearly dependent on V GS I sat = κW n (V GS -V T ) n Propagation delay only has a weak dependence on the supply voltage V DD
CMOS Digital Integrated Circuits 20 CMOS Dynamic Analysis Dynamic Power Dissipation (1/2) The dynamic power dissipation can be derived as follows. P dyn,avg = V DD I DD,avg With I DD,avg taken over one clock period T. The capacitance current which equals the current from the power supply (assuming I Dn = 0 during charging) is Rearranging and integrating over one clock period T Gives I DD,avg T = C load V DD
CMOS Digital Integrated Circuits 21 CMOS Dynamic Analysis Dynamic Power Dissipation (2/2) Solving for I DD,avg and substituting in P avg : It should be noted here the our simple C load may underestimate the power dissipated. In terms of SPICE simulation, the authors’ offer a circuit called power meter.