20 Inverter Chain In Out CL If CL is given: How many stages are needed to minimize the delay?How to size the inverters?May need some additional constraints.
21 Inverter Delay Minimum length devices, L=0.25mm Assume that for WP = 2WN =2Wsame pull-up and pull-down currentsapprox. equal resistances RN = RPapprox. equal rise tpLH and fall tpHL delaysAnalyze as an RC network2WWDelay (D):tpHL = (ln 2) RNCLtpLH = (ln 2) RPCLLoad for the next stage:
22 Inverter with Load RW CL RW tp = k RWCL k is a constant, equal to 0.69 DelayRWCLRWLoad (CL)tp = k RWCLk is a constant, equal to 0.69Assumptions: no load -> zero delayWunit = 1
26 Optimal Tapering for Given N Delay equation has N - 1 unknowns, Cgin,2 – Cgin,NMinimize the delay, find N - 1 partial derivativesResult: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1Size of each stage is the geometric mean of two neighborseach stage has the same effective fanout (Cout/Cin)each stage has the same delay
27 Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f:Effective fanout of each stage:Minimum path delay
28 ExampleInOutCL= 8 C11ff2C1CL/C1 has to be evenly distributed across N = 3 stages:
29 Optimum Number of Stages For a given load, CL and given input capacitance CinFind optimal sizing fFor g = 0, f = e, N = lnF
30 Optimum Effective Fanout f Optimum f for given process defined by gfopt = 3.6for g=1
31 Buffer DesignN f tp2 8 183 4 15164186414166416422.62.88
37 How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic, so ...
38 Minimizing Short-Circuit Power Vdd =3.3Vdd =2.5Vdd =1.5
39 Static Power Consumption Wasted energy …Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)
40 Leakage Currents Sub-threshold current one of most compelling issues in low-energy circuit design!
41 Reverse-Biased Diode Leakage JS = pA/mm2 at 25 deg C for 0.25mm CMOSJS doubles for every 9 deg C!
42 Total Power Consumption Ptot = Pdyn + Pdp + Pstat= (CLVDD + VDD Ipeak ts)f0-1 + VDD IleakIpeak = Maximum short circuit currentTs = 0-100% transition time of IpeakIleak = The current that flows between the supply rails inthe absence of switching activity.2
43 Principles for Power Reduction Prime choice: Reduce voltage!Recent years have seen an acceleration in supply voltage reductionDesign at very low voltages still open question (0.6 … 0.9 V by 2010!)Reduce switching activityReduce physical capacitanceDevice Sizing: for F=20fopt(energy)=3.53, fopt(performance)=4.47
45 Goals of Technology Scaling Make things cheaper:Want to sell more functions (transistors) per chip for the same moneyBuild same products cheaper, sell the same part for less moneyPrice of a transistor has to be reducedBut also want to be faster, smaller, lower power
46 Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%)Double transistor densityReduce energy per transition by 65% (50% power 43% increase in frequencyDie size used to increase by 14% per generationTechnology generation spans 2-3 years
47 Technology Evolution (2000 data) International Technology Roadmap for Semiconductors18617717116013010690Max mP power [W]1.41.26-718019991.7200014.9-3.611-33.5-2Max frequency [GHz],Local-Global126.96.36.199.42.0Bat. power [W]109-10987Wiring levelsSupply [V]304060Technology node [nm]20142011200820042001Year of IntroductionNode years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
49 TerminologyITRS: International Technology Roadmap for Semiconductors. It is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipmentDRAM Half-pitch: The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch has been reduced to 130 nm (.13 micron).
56 mProcessor ScalingP.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
57 mProcessor PowerP.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
58 mProcessor Performance P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
59 2010 Outlook Performance 2X/16 months Size Power 1 TIP (terra instructions/s)30 GHz clockSizeNo of transistors: 2 BillionDie: 40*40 mmPower10kW!!Leakage: 1/3 active PowerP.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
60 Some interesting questions What will cause this model to break?When will it break?Will the model gradually slow down?Power and power densityLeakageProcess Variation