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© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter July 30, 2002

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

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© Digital Integrated Circuits 2nd Inverter Two Inverters Connect in Metal Share power and ground Abut cells

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter: Transient Response t pHL = f(R on.C L ) = 0.69 R on C L V out V R n R p V DD V V in 5 V DD V in 5 0 (a) Low-to-high(b) High-to-low C L C L

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© Digital Integrated Circuits 2nd Inverter Voltage Transfer Characteristic

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Load Characteristics

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC

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© Digital Integrated Circuits 2nd Inverter Switching Threshold as a function of Transistor Ratio 10 0 1 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) W p /W n

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© Digital Integrated Circuits 2nd Inverter Determining V IH and V IL V OH V OL V in V out V M V IL V IH A simplified approach

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© Digital Integrated Circuits 2nd Inverter Gain as a function of VDD

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© Digital Integrated Circuits 2nd Inverter Impact of Process Variations 00.511.522.5 0 0.5 1 1.5 2 2.5 V in (V) V out (V) Good PMOS Bad NMOS Good NMOS Bad PMOS Nominal

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© Digital Integrated Circuits 2nd Inverter Propagation Delay

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay

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© Digital Integrated Circuits 2nd Inverter Transient Response t p = 0.69 C L (R eqn +R eqp )/2 ? t pLH t pHL

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© Digital Integrated Circuits 2nd Inverter Design for Performance Keep capacitances small: C load, C gate, C diff Increase transistor sizes: W/L watch out for self-loading! Increase V DD (????)

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© Digital Integrated Circuits 2nd Inverter Delay as a function of V DD

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© Digital Integrated Circuits 2nd Inverter Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

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© Digital Integrated Circuits 2nd Inverter NMOS/PMOS ratio tpLH tpHL tp = W p /W n

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© Digital Integrated Circuits 2nd Inverter Inverter Sizing

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© Digital Integrated Circuits 2nd Inverter Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

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© Digital Integrated Circuits 2nd Inverter Inverter Delay Minimum length devices, L=0.25 m Assume that for W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t pLH and fall t pHL delays Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay (D): 2W2W W Load for the next stage:

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© Digital Integrated Circuits 2nd Inverter Inverter with Load Load (C L ) Delay Assumptions: no load -> zero delay CLCL t p = k R W C L RWRW RWRW W unit = 1 k is a constant, equal to 0.69

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© Digital Integrated Circuits 2nd Inverter Inverter with Load Load Delay C int CLCL Delay = kR W (C int + C L ) = kR W C int + kR W C L = kR W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) C N = C unit C P = 2C unit 2W2W W

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© Digital Integrated Circuits 2nd Inverter Delay Formula C int = C gin with 1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

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© Digital Integrated Circuits 2nd Inverter Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

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© Digital Integrated Circuits 2nd Inverter Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

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© Digital Integrated Circuits 2nd Inverter Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Minimum path delay Effective fanout of each stage:

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© Digital Integrated Circuits 2nd Inverter Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

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© Digital Integrated Circuits 2nd Inverter Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For = 0, f = e, N = lnF

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© Digital Integrated Circuits 2nd Inverter Optimum Effective Fanout f Optimum f for given process defined by f opt = 3.6 for =1

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© Digital Integrated Circuits 2nd Inverter Buffer Design 1 1 1 1 8 64 4 2.8 8 16 22.6 Nft p 16465 2818 3415 42.815.3

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© Digital Integrated Circuits 2nd Inverter Power Dissipation

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© Digital Integrated Circuits 2nd Inverter Where Does Power Go in CMOS?

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© Digital Integrated Circuits 2nd Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

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© Digital Integrated Circuits 2nd Inverter Node Transition Activity and Power

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© Digital Integrated Circuits 2nd Inverter Short Circuit Currents

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© Digital Integrated Circuits 2nd Inverter How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can’t do this for cascade logic, so...

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© Digital Integrated Circuits 2nd Inverter Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

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© Digital Integrated Circuits 2nd Inverter Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

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© Digital Integrated Circuits 2nd Inverter Leakage Currents Sub-threshold current one of most compelling issues in low-energy circuit design!

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© Digital Integrated Circuits 2nd Inverter Reverse-Biased Diode Leakage JS = 10-100 pA/ m2 at 25 deg C for 0.25 m CMOS JS doubles for every 9 deg C!

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© Digital Integrated Circuits 2nd Inverter Total Power Consumption P tot = P dyn + P dp + P stat = (C L V DD + V DD I peak t s )f 0-1 + V DD I leak Ipeak = Maximum short circuit current Ts= 0-100% transition time of Ipeak Ileak = The current that flows between the supply rails in the absence of switching activity. 2

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© Digital Integrated Circuits 2nd Inverter Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47

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© Digital Integrated Circuits 2nd Inverter Impact of Technology Scaling

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© Digital Integrated Circuits 2nd Inverter Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced But also want to be faster, smaller, lower power

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© Digital Integrated Circuits 2nd Inverter Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 2-3 years

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© Digital Integrated Circuits 2nd Inverter Technology Evolution (2000 data) International Technology Roadmap for Semiconductors 18617717116013010690 Max P power [W] 1.4 1.2 6-7 1.5-1.8 180 1999 1.7 1.6-1.4 6-7 1.5-1.8 2000 14.9 -3.6 11-37.1-2.53.5-22.1-1.6 Max frequency [GHz],Local-Global 2.52.32.12.42.0Bat. power [W] 109-10987Wiring levels 0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V] 30406090130 Technology node [nm] 20142011200820042001 Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

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© Digital Integrated Circuits 2nd Inverter ITRS Technology Roadmap

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© Digital Integrated Circuits 2nd Inverter Terminology ITRS: International Technology Roadmap for Semiconductors. It is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment DRAM Half-pitch: The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch has been reduced to 130 nm (.13 micron).

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© Digital Integrated Circuits 2nd Inverter Half Pitch

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© Digital Integrated Circuits 2nd Inverter Technology Scaling (1) Minimum Feature Size Propagation Delay t p decreases by 13%/year 50% every 5 years!

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© Digital Integrated Circuits 2nd Inverter Technology Scaling (2) Number of components per chip

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© Digital Integrated Circuits 2nd Inverter Technology Scaling Models

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© Digital Integrated Circuits 2nd Inverter Scaling Relationships for Long Channel Devices

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© Digital Integrated Circuits 2nd Inverter Transistor Scaling (velocity-saturated devices)

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© Digital Integrated Circuits 2nd Inverter Processor Scaling P.Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter Processor Power P.Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter Processor Performance P.Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter 2010 Outlook Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 active Power P.Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter Some interesting questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation

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