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© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter July 30, 2002.

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Presentation on theme: "© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter July 30, 2002."— Presentation transcript:

1 © Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter July 30, 2002

2 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

3 © Digital Integrated Circuits 2nd Inverter Two Inverters Connect in Metal Share power and ground Abut cells

4 © Digital Integrated Circuits 2nd Inverter CMOS Inverter: Transient Response t pHL = f(R on.C L ) = 0.69 R on C L V out V R n R p V DD V V in 5 V DD V in 5 0 (a) Low-to-high(b) High-to-low C L C L

5 © Digital Integrated Circuits 2nd Inverter Voltage Transfer Characteristic

6 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Load Characteristics

7 © Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC

8 © Digital Integrated Circuits 2nd Inverter Switching Threshold as a function of Transistor Ratio M V (V) W p /W n

9 © Digital Integrated Circuits 2nd Inverter Determining V IH and V IL V OH V OL V in V out V M V IL V IH A simplified approach

10 © Digital Integrated Circuits 2nd Inverter Gain as a function of VDD

11 © Digital Integrated Circuits 2nd Inverter Impact of Process Variations V in (V) V out (V) Good PMOS Bad NMOS Good NMOS Bad PMOS Nominal

12 © Digital Integrated Circuits 2nd Inverter Propagation Delay

13 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay

14 © Digital Integrated Circuits 2nd Inverter Transient Response t p = 0.69 C L (R eqn +R eqp )/2 ? t pLH t pHL

15 © Digital Integrated Circuits 2nd Inverter Design for Performance  Keep capacitances small: C load, C gate, C diff  Increase transistor sizes: W/L  watch out for self-loading!  Increase V DD (????)

16 © Digital Integrated Circuits 2nd Inverter Delay as a function of V DD

17 © Digital Integrated Circuits 2nd Inverter Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

18 © Digital Integrated Circuits 2nd Inverter NMOS/PMOS ratio tpLH tpHL tp  = W p /W n

19 © Digital Integrated Circuits 2nd Inverter Inverter Sizing

20 © Digital Integrated Circuits 2nd Inverter Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

21 © Digital Integrated Circuits 2nd Inverter Inverter Delay Minimum length devices, L=0.25  m Assume that for W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t pLH and fall t pHL delays Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay (D): 2W2W W Load for the next stage:

22 © Digital Integrated Circuits 2nd Inverter Inverter with Load Load (C L ) Delay Assumptions: no load -> zero delay CLCL t p = k R W C L RWRW RWRW W unit = 1 k is a constant, equal to 0.69

23 © Digital Integrated Circuits 2nd Inverter Inverter with Load Load Delay C int CLCL Delay = kR W (C int + C L ) = kR W C int + kR W C L = kR W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) C N = C unit C P = 2C unit 2W2W W

24 © Digital Integrated Circuits 2nd Inverter Delay Formula C int =  C gin with   1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

25 © Digital Integrated Circuits 2nd Inverter Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

26 © Digital Integrated Circuits 2nd Inverter Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

27 © Digital Integrated Circuits 2nd Inverter Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Minimum path delay Effective fanout of each stage:

28 © Digital Integrated Circuits 2nd Inverter Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

29 © Digital Integrated Circuits 2nd Inverter Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For  = 0, f = e, N = lnF

30 © Digital Integrated Circuits 2nd Inverter Optimum Effective Fanout f Optimum f for given process defined by  f opt = 3.6 for  =1

31 © Digital Integrated Circuits 2nd Inverter Buffer Design Nft p

32 © Digital Integrated Circuits 2nd Inverter Power Dissipation

33 © Digital Integrated Circuits 2nd Inverter Where Does Power Go in CMOS?

34 © Digital Integrated Circuits 2nd Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

35 © Digital Integrated Circuits 2nd Inverter Node Transition Activity and Power

36 © Digital Integrated Circuits 2nd Inverter Short Circuit Currents

37 © Digital Integrated Circuits 2nd Inverter How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can’t do this for cascade logic, so...

38 © Digital Integrated Circuits 2nd Inverter Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

39 © Digital Integrated Circuits 2nd Inverter Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

40 © Digital Integrated Circuits 2nd Inverter Leakage Currents Sub-threshold current one of most compelling issues in low-energy circuit design!

41 © Digital Integrated Circuits 2nd Inverter Reverse-Biased Diode Leakage JS = pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!

42 © Digital Integrated Circuits 2nd Inverter Total Power Consumption P tot = P dyn + P dp + P stat = (C L V DD + V DD I peak t s )f V DD I leak Ipeak = Maximum short circuit current Ts= 0-100% transition time of Ipeak Ileak = The current that flows between the supply rails in the absence of switching activity. 2

43 © Digital Integrated Circuits 2nd Inverter Principles for Power Reduction  Prime choice: Reduce voltage!  Recent years have seen an acceleration in supply voltage reduction  Design at very low voltages still open question (0.6 … 0.9 V by 2010!)  Reduce switching activity  Reduce physical capacitance  Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47

44 © Digital Integrated Circuits 2nd Inverter Impact of Technology Scaling

45 © Digital Integrated Circuits 2nd Inverter Goals of Technology Scaling  Make things cheaper:  Want to sell more functions (transistors) per chip for the same money  Build same products cheaper, sell the same part for less money  Price of a transistor has to be reduced  But also want to be faster, smaller, lower power

46 © Digital Integrated Circuits 2nd Inverter Technology Scaling  Goals of scaling the dimensions by 30%:  Reduce gate delay by 30% (increase operating frequency by 43%)  Double transistor density  Reduce energy per transition by 65% (50% power 43% increase in frequency  Die size used to increase by 14% per generation  Technology generation spans 2-3 years

47 © Digital Integrated Circuits 2nd Inverter Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Max  P power [W] Max frequency [GHz],Local-Global Bat. power [W] Wiring levels Supply [V] Technology node [nm] Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

48 © Digital Integrated Circuits 2nd Inverter ITRS Technology Roadmap

49 © Digital Integrated Circuits 2nd Inverter Terminology  ITRS: International Technology Roadmap for Semiconductors. It is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment  DRAM Half-pitch: The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch has been reduced to 130 nm (.13 micron).

50 © Digital Integrated Circuits 2nd Inverter Half Pitch

51 © Digital Integrated Circuits 2nd Inverter Technology Scaling (1) Minimum Feature Size Propagation Delay t p decreases by 13%/year 50% every 5 years!

52 © Digital Integrated Circuits 2nd Inverter Technology Scaling (2) Number of components per chip

53 © Digital Integrated Circuits 2nd Inverter Technology Scaling Models

54 © Digital Integrated Circuits 2nd Inverter Scaling Relationships for Long Channel Devices

55 © Digital Integrated Circuits 2nd Inverter Transistor Scaling (velocity-saturated devices)

56 © Digital Integrated Circuits 2nd Inverter  Processor Scaling P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

57 © Digital Integrated Circuits 2nd Inverter  Processor Power P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

58 © Digital Integrated Circuits 2nd Inverter  Processor Performance P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

59 © Digital Integrated Circuits 2nd Inverter 2010 Outlook  Performance 2X/16 months  1 TIP (terra instructions/s)  30 GHz clock  Size  No of transistors: 2 Billion  Die: 40*40 mm  Power  10kW!!  Leakage: 1/3 active Power P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

60 © Digital Integrated Circuits 2nd Inverter Some interesting questions  What will cause this model to break?  When will it break?  Will the model gradually slow down?  Power and power density  Leakage  Process Variation


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