Presentation on theme: "9/15/05ELEC5970-001/6970-001 Lecture 71 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits."— Presentation transcript:
9/15/05ELEC / Lecture 71 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power: Transistor Sizing Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University
9/15/05ELEC / Lecture 72 Delay of a CMOS Gate CMOS gate CLCL CgCg C int Propagation delay through the gate: t p = 0.69 R eq (C int + C L ) ≈ 0.69 R eq C g (1 + C L /C g ) = t p0 (1 + C L /C g ) Gate capacitance Intrinsic capacitance
9/15/05ELEC / Lecture 73 R eq, C g, C int, and Width Sizing R eq : equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = sizing factor C g : gate capacitance, proportional to C ox WL; scales as S C int : intrinsic output capacitance ≈ C g, for submicron processes t p0 : intrinsic delay = 0.69R eq C g ; independent of sizing
9/15/05ELEC / Lecture 74 Effective Fan-out, f Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: f=C L /C g t p =t p0 (1 + f )
9/15/05ELEC / Lecture 75 Sizing an Inverter Chain Cg1Cg1 Cg2Cg2 CLCL 12N C g2 = f2C g1 t p1 = t p0 (1 + C g2 /C g1 ) t p2 = t p0 (1 + C g3 /C g2 )N t p =Σ t pj =t p0 Σ (1 + C gj+1 /C gj ) j=1j=1
9/15/05ELEC / Lecture 76 Minimum Delay Sizing Equate partial derivatives of t p with respect to C gj to 0: 1/C g1 – C g3 /C g2 2 = 0, etc. C g2 2 = C g1 ×C g3, etc. C g2 /C g1 = C g3 /C g2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: C L /C g1 = F = f N, t p = Nt p0 (1 + F 1/N )
9/15/05ELEC / Lecture 77 Minimum Delay Sizing Equate partial derivatives of t p with respect to N to 0: dNt p0 (1 + F 1/N ) ───────── = 0 dN i.e. F 1/N – F 1/N (ln F)/N = 0 or ln f = 1 → f = e = 2.7 and N = ln F
9/15/05ELEC / Lecture 78 Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003.
9/15/05ELEC / Lecture 79 Sizing for Energy Minimization Cg1Cg1 CLCL t p = t p0 [(1+f) + (1+F/f )] = t p0 (2+ f + F/f ) F= C L /C g1 t p0 ~V DD /(V DD - V t ) Energy dissipation, E = V DD 2 C g1 (1 + f + F ) f 1
9/15/05ELEC / Lecture 710 Holding Delay Constant Reference circuit: f = 1, supply voltage = V ref Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: t p t p0 (2+f+F/f ) V DD V ref -V t 2+f+F/f ── = ──────── = ── ──── ───── ≤ 1 t pref t p0ref (3+F ) V ref V DD -V t 3+F
9/15/05ELEC / Lecture 711 Supply Voltage Vs. Sizing f V DD (volts) F= f opt ≈ √F V ref = 2.5V V t = 0.5V
9/15/05ELEC / Lecture 712 Energy E V DD f + F ── = ─── ────── E ref V ref F
9/15/05ELEC / Lecture 713 Normalized Energy Vs. Sizing f Normalized Energy F= f opt ≈ √F V ref = 2.5V V t = 0.5V
9/15/05ELEC / Lecture 714 Summary Device sizing combined with supply voltage reduction reduces energy consumption. For large fan-out energy reduction by a factor of 10 is possible. An exception is F = 1 case, where the minimum size device is also the most effective one. Oversizing the devices increases energy consumption.