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Lecture 5: DC & Transient Response

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response2 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response3 Pass Transistors We have assumed source is grounded What if source > 0? –e.g. pass transistor passing V DD V g = V DD –If V s > V DD -V t, V gs < V t –Hence transistor would turn itself off nMOS pass transistors pull no higher than V DD -V tn –Called a degraded “1” –Approach degraded value slowly (low I ds ) pMOS pass transistors pull no lower than V tp Transmission gates are needed to pass both 0 and 1

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response4 Pass Transistor Ckts

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response5 DC Response DC Response: V out vs. V in for a gate Ex: Inverter –When V in = 0 -> V out = V DD –When V in = V DD -> V out = 0 –In between, V out depends on transistor size and current –By KCL, must settle such that I dsn = |I dsp | –We could solve equations –But graphical solution gives more insight

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response6 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in –Cutoff? –Linear? –Saturation?

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response7 nMOS Operation CutoffLinearSaturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn V gsn = V in V dsn = V out

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response8 pMOS Operation CutoffLinearSaturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp – V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp – V tp V out < V in - V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response9 I-V Characteristics Make pMOS is wider than nMOS such that n = p

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response10 Current vs. V out, V in

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response11 Load Line Analysis For a given V in : –Plot I dsn, I dsp vs. V out –V out must be where |currents| are equal in

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response12 Load Line Analysis V in = 0 0.2V DD 0.4V DD 0.6V DD 0.8V DD V DD

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response13 DC Transfer Curve Transcribe points onto V in vs. V out plot

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response14 Operating Regions Revisit transistor operating regions RegionnMOSpMOS ACutoffLinear BSaturationLinear CSaturation DLinearSaturation ELinearCutoff

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response15 Beta Ratio If p / n 1, switching point will move from V DD /2 Called skewed gate Other gates: collapse into equivalent inverter

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response16 Noise Margins How much noise can a gate input see before it does not recognize the input?

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response17 Logic Levels To maximize noise margins, select logic levels at –unity gain point of DC transfer characteristic

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response18 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes –Requires solving differential equations Input is usually considered to be a step or ramp –From 0 to V DD or vice versa

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response19 Inverter Step Response Ex: find step response of inverter driving load cap

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response20 Delay Definitions t pdr : rising propagation delay –From input to rising output crossing V DD /2 t pdf : falling propagation delay –From input to falling output crossing V DD /2 t pd : average propagation delay –t pd = (t pdr + t pdf )/2 t r : rise time –From output crossing 0.2 V DD to 0.8 V DD t f : fall time –From output crossing 0.8 V DD to 0.2 V DD

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response21 Delay Definitions t cdr : rising contamination delay –From input to rising output crossing V DD /2 t cdf : falling contamination delay –From input to falling output crossing V DD /2 t cd : average contamination delay –t pd = (t cdr + t cdf )/2

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response22 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically –Uses more accurate I-V models too! But simulations take time to write, may hide insight

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response23 Delay Estimation We would like to be able to easily estimate delay –Not as accurate as simulation –But easier to ask “What if?” The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay –C = total capacitance on output node –Use effective resistance R –So that t pd = RC Characterize transistors by finding their effective R –Depends on average current as gate switches

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response24 Effective Resistance Shockley models have limited value –Not accurate enough for modern transistors –Too complicated for much hand analysis Simplification: treat transistor as resistor –Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R –R averaged across switching of digital gate Too inaccurate to predict current at any given time –But good enough to predict RC delay

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response25 RC Delay Model Use equivalent circuits for MOS transistors –Ideal switch + capacitance and ON resistance –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response26 RC Values Capacitance –C = C g = C s = C d = 2 fF/ m of gate width in 0.6 m –Gradually decline to 1 fF/ m in nanometer techs. Resistance –R 6 K * m in 0.6 m process –Improves with shorter channel lengths Unit transistors –May refer to minimum contacted device (4/2 ) –Or maybe 1 m wide device –Doesn’t matter as long as you are consistent

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response27 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter d = 6RC

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response28 Delay Model Comparison

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response29 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R)

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response30 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response31 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response32 Example: 3-input NAND Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates.

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response33 Delay Components Delay has two parts –Parasitic delay 9 or 11 RC Independent of load –Effort delay 5h RC Proportional to load capacitance

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response34 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If all three inputs fall simultaneously

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response35 Diffusion Capacitance We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact –Reduces output capacitance by 2C –Merged uncontacted diffusion might help too

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CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response36 Layout Comparison Which layout is better?

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