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Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture notes)

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CMOS VLSI Design4: DC and Transient ResponseSlide 2 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation

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CMOS VLSI Design4: DC and Transient ResponseSlide 3 Activity 1) If the width of a transistor increases, the current will increasedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increases, its gate capacitance will increasedecreasenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change

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CMOS VLSI Design4: DC and Transient ResponseSlide 4 Activity 1) If the width of a transistor increases, the current will increasedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increases, its gate capacitance will increasedecreasenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change

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CMOS VLSI Design4: DC and Transient ResponseSlide 5 DC Response DC Response: V out vs. V in for a gate Ex: Inverter –When V in = 0 -> V out = V DD –When V in = V DD -> V out = 0 –In between, V out depends on transistor size and current –By KCL, must settle such that I dsn = |I dsp | –We could solve equations –But graphical solution gives more insight

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CMOS VLSI Design4: DC and Transient ResponseSlide 6 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in –Cutoff? –Linear? –Saturation?

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CMOS VLSI Design4: DC and Transient ResponseSlide 7 nMOS Operation CutoffLinearSaturated V gsn <V gsn > V dsn < V gsn > V dsn >

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CMOS VLSI Design4: DC and Transient ResponseSlide 8 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn

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CMOS VLSI Design4: DC and Transient ResponseSlide 9 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn V gsn = V in V dsn = V out

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CMOS VLSI Design4: DC and Transient ResponseSlide 10 nMOS Operation CutoffLinearSaturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn V gsn = V in V dsn = V out

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CMOS VLSI Design4: DC and Transient ResponseSlide 11 pMOS Operation CutoffLinearSaturated V gsp >V gsp < V dsp > V gsp < V dsp <

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CMOS VLSI Design4: DC and Transient ResponseSlide 12 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp

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CMOS VLSI Design4: DC and Transient ResponseSlide 13 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0

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CMOS VLSI Design4: DC and Transient ResponseSlide 14 pMOS Operation CutoffLinearSaturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp – V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp – V tp V out < V in - V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0

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CMOS VLSI Design4: DC and Transient ResponseSlide 15 I-V Characteristics Make pMOS is wider than nMOS such that n = p

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CMOS VLSI Design4: DC and Transient ResponseSlide 16 Current vs. V out, V in

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CMOS VLSI Design4: DC and Transient ResponseSlide 17 Load Line Analysis For a given V in : –Plot I dsn, I dsp vs. V out –V out must be where |currents| are equal in

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CMOS VLSI Design4: DC and Transient ResponseSlide 18 Load Line Analysis V in = 0

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CMOS VLSI Design4: DC and Transient ResponseSlide 19 Load Line Analysis V in = 0.2V DD

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CMOS VLSI Design4: DC and Transient ResponseSlide 20 Load Line Analysis V in = 0.4V DD

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CMOS VLSI Design4: DC and Transient ResponseSlide 21 Load Line Analysis V in = 0.6V DD

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CMOS VLSI Design4: DC and Transient ResponseSlide 22 Load Line Analysis V in = 0.8V DD

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CMOS VLSI Design4: DC and Transient ResponseSlide 23 Load Line Analysis V in = V DD

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CMOS VLSI Design4: DC and Transient ResponseSlide 24 Load Line Summary

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CMOS VLSI Design4: DC and Transient ResponseSlide 25 DC Transfer Curve Transcribe points onto V in vs. V out plot

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CMOS VLSI Design4: DC and Transient ResponseSlide 26 Operating Regions Revisit transistor operating regions RegionnMOSpMOS A B C D E

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CMOS VLSI Design4: DC and Transient ResponseSlide 27 Operating Regions Revisit transistor operating regions RegionnMOSpMOS ACutoffLinear BSaturationLinear CSaturation DLinearSaturation ELinearCutoff

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CMOS VLSI Design4: DC and Transient ResponseSlide 28 Beta Ratio If p / n 1, switching point will move from V DD /2 Called skewed gate Other gates: collapse into equivalent inverter

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CMOS VLSI Design4: DC and Transient ResponseSlide 29 Noise Margins How much noise can a gate input see before it does not recognize the input?

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CMOS VLSI Design4: DC and Transient ResponseSlide 30 Logic Levels To maximize noise margins, select logic levels at

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CMOS VLSI Design4: DC and Transient ResponseSlide 31 Logic Levels To maximize noise margins, select logic levels at –unity gain point of DC transfer characteristic

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CMOS VLSI Design4: DC and Transient ResponseSlide 32 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes –Requires solving differential equations Input is usually considered to be a step or ramp –From 0 to V DD or vice versa

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CMOS VLSI Design4: DC and Transient ResponseSlide 33 Inverter Step Response Ex: find step response of inverter driving load cap

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CMOS VLSI Design4: DC and Transient ResponseSlide 34 Inverter Step Response Ex: find step response of inverter driving load cap

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CMOS VLSI Design4: DC and Transient ResponseSlide 35 Inverter Step Response Ex: find step response of inverter driving load cap

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CMOS VLSI Design4: DC and Transient ResponseSlide 36 Inverter Step Response Ex: find step response of inverter driving load cap

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CMOS VLSI Design4: DC and Transient ResponseSlide 37 Inverter Step Response Ex: find step response of inverter driving load cap

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CMOS VLSI Design4: DC and Transient ResponseSlide 38 Inverter Step Response Ex: find step response of inverter driving load cap

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CMOS VLSI Design4: DC and Transient ResponseSlide 39 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time

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CMOS VLSI Design4: DC and Transient ResponseSlide 40 Delay Definitions t pdr : rising propagation delay –From input to rising output crossing V DD /2 (upper bound) t pdf : falling propagation delay –From input to falling output crossing V DD /2 (upper bound) t pd : average propagation delay –t pd = (t pdr + t pdf )/2 t r : rise time –From output crossing 0.2 V DD to 0.8 V DD t f : fall time –From output crossing 0.8 V DD to 0.2 V DD

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CMOS VLSI Design4: DC and Transient ResponseSlide 41 Delay Definitions t cdr : rising contamination delay –From input beginning to change to output beginning to rise (lower bound) t cdf : falling contamination delay –From input beginning to change to output beginning to fall (lower bound) t cd : average contamination delay –t pd = (t cdr + t cdf )/2

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CMOS VLSI Design4: DC and Transient ResponseSlide 42 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically –Uses more accurate I-V models too! But simulations do take time to complete for large circuits

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CMOS VLSI Design4: DC and Transient ResponseSlide 43 Delay Estimation We would like to be able to easily estimate delay –Not as accurate as simulation –But easier to ask “What if?” The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay –C = total capacitance on output node –Use effective resistance R –So that t pd = RC Characterize transistors by finding their effective R –Depends on average current as gate switches

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CMOS VLSI Design4: DC and Transient ResponseSlide 44 RC Delay Models Use equivalent circuits for MOS transistors –Ideal switch + capacitance and ON resistance –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width

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CMOS VLSI Design4: DC and Transient ResponseSlide 45 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

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CMOS VLSI Design4: DC and Transient ResponseSlide 46 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

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CMOS VLSI Design4: DC and Transient ResponseSlide 47 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

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CMOS VLSI Design4: DC and Transient ResponseSlide 48 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

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CMOS VLSI Design4: DC and Transient ResponseSlide 49 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

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CMOS VLSI Design4: DC and Transient ResponseSlide 50 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

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CMOS VLSI Design4: DC and Transient ResponseSlide 51 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder

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CMOS VLSI Design4: DC and Transient ResponseSlide 52 Example: 2-input NAND Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates.

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CMOS VLSI Design4: DC and Transient ResponseSlide 53 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

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CMOS VLSI Design4: DC and Transient ResponseSlide 54 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

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CMOS VLSI Design4: DC and Transient ResponseSlide 55 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

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CMOS VLSI Design4: DC and Transient ResponseSlide 56 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

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CMOS VLSI Design4: DC and Transient ResponseSlide 57 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

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CMOS VLSI Design4: DC and Transient ResponseSlide 58 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

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CMOS VLSI Design4: DC and Transient ResponseSlide 59 Delay Components Delay has two parts –Parasitic delay 6 or 7 RC Independent of load –Effort delay 4h RC Proportional to load capacitance

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CMOS VLSI Design4: DC and Transient ResponseSlide 60 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously

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CMOS VLSI Design4: DC and Transient ResponseSlide 61 Diffusion Capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact –Reduces output capacitance by 2C –Merged uncontacted diffusion might help too

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CMOS VLSI Design4: DC and Transient ResponseSlide 62 Layout Comparison Which layout is better?

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