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Delay Calculations Section

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Load Capacitance Calculation C load =C self +C wire +C fanout

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Fanout Capacitance

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Fanout Gate Capacitance C fanout : fanout capacitance due to the inputs of subsequent gates, C G. C fanout =C G1 +C G2 +C G3 …. Assumption: Each fanout is an inverter.

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Input Capacitance Calculation C OL : overlap capacitance C GN, C GP : Thin Oxide Capacitance

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Worst Case Analysis Assumption The thin-oxide capacitance is voltage dependent. The worst case analysis uses C ox WL to compute its worst case value.

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Thin Oxide Capacitance:C g C G =WLC ox =WL(ε ox /t ox )=WC g Unit of C g : fF/μm [Worst Case Analysis]

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CgCg toxLCg 110 nm51.61 fF/μm 7.5 nm0.35 μm1.65 fF/μm 2.2 nm0.1 μm1.61 fF/μm Cg is approximately 1.61 fF/μm for the last 25 years. Exception: the 0.18 μm process, which has a Cg of 1.0 fF/ μm. [Worst Case Analysis]

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Thin Oxide Capacitance:C ol

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Components of C ol C ol =C f +C ov C f :fringing capacitance C ov : overlap capacitance

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Redefine C g For 0.13 μm, – C g (due to t ox alone): 1.6 fF/μm [Hodges, p.72] – C ol (due to C ov and C f ): 0.25 fF/ μm [Hodges, p.80] – Redefine Cg [Hodges, p.259] as C g =C ox L+2C ol C g =1.6 fF/μm fF/μm=2 fF/μm C g has been constant for over 20 years – Multipy Cg by W to obtain the total capacitance due to t ox, C ov and C f [Worst Case Analysis]

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Gate Capacitance of an Inverter C G =C g (W n +W p ) C G =2fF/μm(W n +W p ) [Worst Case Analysis]

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Input Capacitance of a 3-input NAND Gate 2W 3W C G =C g (W n +W p )=C g (3W+2W)= C g (5W)

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Fanout Gate capacitance of n Inverters C fanout =2fF/μm[(W n +W p ) 1 +(W n +W p ) 2 …(W n +W p ) n ] [Worst Case Analysis] For NANDs, NORs, apply the above equation with appropiate widths.

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Self-Capacitance Calculation 1.Eliminate capacitors not connected to the output 2.Assume the transistors are either on (Saturation) or off (Cutoff). 3.C GD is negligible in either saturation or cutoff.

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Calculation of Self-Capacitance of an Inverter C self =C DBn +C DBP +2C OL +2C OL C DBn =C jn W n C DBp =C jp W p C OL =C ol W C self =C jn W n +C jp W p +2C ol (W n +W p ) Assume C jn =C jp C self =C eff (W n +W p ) For 0.13: C eff =1 fF/μm [Hodges, p. 261]

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Self-Capacitance of a NOR Condition: A=0 B=0→1 CDB4, CSB3 do not need to be charged.→NOT THE WORST CASE CDB3 is charged, while CDB1 and CDB2 are discharged. To avoid double counting, CDB1 and CDB2 will be called CDB12.

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Self-Capacitance of NOR Constant Voltage at X

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Self-Capacitance of a NOR CDB4 and CSB3 need to be charged CDB3 is charged, while CDB1 and CDB2 are discharged WORST CASE!!

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Self-Capacitance of NOR WORST CASE!!

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Wire Capacitance Ignore wire capacitance if the length of a wire is less than a few microns. Include wires longer than a few microns – C wire =C int L wire – C int =0.2 fF/um For very long wires use distributed model

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Example 6.4 Capacitance Calculation for Inverter

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Propagation Delay

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Conclusion Propagation delay depends on the arrival time of inputs – In a series stack, the delay increases as the late arriving input is further from the output.

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Sequence: A: charges X B: charges Y C: discharges X, Y, CL Worst Case

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Sequence: C: discharges X, (if any) B: discharges Y (if any) A: discharges CL Improved!

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Design Strategy 1 Reorder the inputs so that – the earliest signal arrive lower in the stack – The latest signals arrive near the top of the stack

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Design Strategy 2 To reduce delay: – W C >W B >W A Problem: – Device capacitance are increased as the device sizes are increased.

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Delay Calculation with Input Slope

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Improve Delay Calculation with Input Slope i out =i NMOS -i PMOS 1.Select V in and V out 2.Calculate i NMOS and i PMOS 3.Calculate i out

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Inverter Output Current as a function of V out and V in

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Simplified Inverter Output Current as a function of V out and V in

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Example 6.5 Compute the delay (t PHL,step ) of a CMOS inverter due to a step input Compute the delay (t PHL,step ) of a CMOS inverter due to an input ramp with a rise time of t r

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Conclusion from Example 6.5 t ramp =Δt ramp +t step t step =0.7RC Δt ramp depends on the t r of the driving circuit. Δt ramp =0.7RC/2=0.3RC Assumption: the t r is equal to 2t PLH

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Inverter Chain Delay for a Ramp Input

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Example 6.6

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