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CMOS VLSI Design DC Transfer Characteristics and Switch –level RC delay Models.

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Presentation on theme: "CMOS VLSI Design DC Transfer Characteristics and Switch –level RC delay Models."— Presentation transcript:

1 CMOS VLSI Design DC Transfer Characteristics and Switch –level RC delay Models

2 CMOS VLSI DesignSlide 2 DC Response  DC Response: V out vs. V in for a gate  Ex: Inverter –When V in = 0 -> V out = V DD –When V in = V DD -> V out = 0 –In between, V out depends on transistor size and current –By KCL, must settle such that I dsn = |I dsp | –We could solve equations –But graphical solution gives more insight

3 CMOS VLSI DesignSlide 3 Transistor Operation  Current depends on region of transistor behavior  For what V in and V out are nMOS and pMOS in –Cutoff? –Linear? –Saturation?

4 CMOS VLSI DesignSlide 4 nMOS Operation CutoffLinearSaturated V gsn V dsn < V gsn > V dsn >

5 CMOS VLSI DesignSlide 5 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn

6 CMOS VLSI DesignSlide 6 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn V gsn = V in V dsn = V out

7 CMOS VLSI DesignSlide 7 nMOS Operation CutoffLinearSaturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn V gsn = V in V dsn = V out

8 CMOS VLSI DesignSlide 8 pMOS Operation CutoffLinearSaturated V gsp >V gsp < V dsp > V gsp < V dsp <

9 CMOS VLSI DesignSlide 9 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp

10 CMOS VLSI DesignSlide 10 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0

11 CMOS VLSI DesignSlide 11 pMOS Operation CutoffLinearSaturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp – V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp – V tp V out < V in - V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0

12 CMOS VLSI DesignSlide 12 I-V Characteristics  Make pMOS is wider than nMOS such that  n =  p

13 CMOS VLSI DesignSlide 13 Current vs. V out, V in plot absolute value of pMOS

14 CMOS VLSI DesignSlide 14 Load Line Analysis  For a given V in : –Plot I dsn, I dsp vs. V out –V out must be where |currents| are equal in

15 CMOS VLSI DesignSlide 15 Load Line Analysis  V in = 0

16 CMOS VLSI DesignSlide 16 Load Line Analysis  V in = 0.2V DD

17 CMOS VLSI DesignSlide 17 Load Line Analysis  V in = 0.4V DD

18 CMOS VLSI DesignSlide 18 Load Line Analysis  V in = 0.6V DD

19 CMOS VLSI DesignSlide 19 Load Line Analysis  V in = 0.8V DD

20 CMOS VLSI DesignSlide 20 Load Line Analysis  V in = V DD

21 CMOS VLSI DesignSlide 21 Load Line Summary

22 CMOS VLSI DesignSlide 22 DC Transfer Curve  Transcribe points onto V in vs. V out plot

23 CMOS VLSI DesignSlide 23 Operating Regions  Revisit transistor operating regions RegionnMOSpMOS A B C D E

24 CMOS VLSI DesignSlide 24 Operating Regions  Revisit transistor operating regions RegionnMOSpMOS ACutoffLinear BSaturationLinear CSaturation DLinearSaturation ELinearCutoff

25 CMOS VLSI DesignSlide 25 Beta Ratio  If  p /  n  1, switching point will move from V DD /2  If  p /  n < 1, the inverter is LO-skewed  If  p /  n > 1, the inverter is HI-skewed

26 CMOS VLSI DesignSlide 26 Noise Margins  How much noise can a gate input see before it does not recognize the input? NM H = V OH -V IH NM L = V IL - V OL

27 CMOS VLSI DesignSlide 27 Logic Levels  To maximize noise margins, select logic levels at

28 CMOS VLSI DesignSlide 28 Logic Levels  To maximize noise margins, select logic levels at –unity gain point of DC transfer characteristic

29 CMOS VLSI DesignSlide 29 Pass Transistors  We have assumed source is grounded  What if source > 0? –e.g. pass transistor passing V DD

30 CMOS VLSI DesignSlide 30 Pass Transistors  We have assumed source is grounded  What if source > 0? –e.g. pass transistor passing V DD  V g = V DD –If V s > V DD -V t, V gs < V t –Hence transistor would turn itself off  nMOS pass transistors pull no higher than V DD -V tn –Called a degraded “1” –Approach degraded value slowly (low I ds )  pMOS pass transistors pull no lower than V tp

31 CMOS VLSI DesignSlide 31 Pass Transistor Ckts

32 CMOS VLSI DesignSlide 32 Pass Transistor Ckts

33 CMOS VLSI DesignSlide 33

34 CMOS VLSI DesignSlide 34 Tristate Inverter Why (d) is a bad design? If EN = 0, Y is supposed to be float, but if A changes, charge at internal node may disturb node Y. more in section 6.3.4)

35 CMOS VLSI DesignSlide 35 Effective Resistance  Shockley models have limited value –Not accurate enough for modern transistors –Too complicated for much hand analysis  Simplification: treat transistor as resistor –Replace I ds (V ds, V gs ) with effective resistance R –I ds = V ds /R –R averaged across switching of digital gate  Too inaccurate to predict current at any given time –But good enough to predict RC delay

36 CMOS VLSI DesignSlide 36

37 CMOS VLSI DesignSlide 37 RC Delay Model  Use equivalent circuits for MOS transistors –Ideal switch + capacitance and ON resistance –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C  Capacitance proportional to width  Resistance inversely proportional to width

38 CMOS VLSI DesignSlide 38 A nMOS transistor of unit size: minimum length and minimum contacted diffusion width, size = 1 means that W = 4, L = 2, W/L = 2 A nMOS transistor size = k

39 CMOS VLSI DesignSlide 39 Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C

40 CMOS VLSI DesignSlide 40 RC Values  Capacitance –C = C g = C s = C d = 2 fF/  m of gate width –Values similar across many processes  Resistance –R  6 K  /  m in 0.6um process –Improves with shorter channel lengths  Unit transistors –May refer to minimum contacted device (4/2 ) –Or maybe 1  m wide device –Doesn’t matter as long as you are consistent

41 CMOS VLSI DesignSlide 41 Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter

42 CMOS VLSI DesignSlide 42 Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter

43 CMOS VLSI DesignSlide 43 Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter

44 CMOS VLSI DesignSlide 44 Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter d = 6RC


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