2 Latches A “memory” logic circuit that can maintain a constant output value. Achieved by the use of feedback whereby the output is connected to the inputs in such a way to reinforce the output value.
3 Suppose an AND gate has 1’s on its inputs. This produces a 1 on the output. If this 1 is fed back to create a 1 on an input with the other inputs kept at 1, the output will maintain a 1 output: Potential memory design If the output was initially a 0, a 0 would be fed back and reinforce and maintain the 0 output. However then no way to make output a 1.
4 To force output to become either a 0 or a 1 requires a circuit such as: Set–reset memory design Reset (bar) Set (bar)
5 Latch memory design with true and complementary outputs Just the previous circuit re-drawn in the more conventional manner
6 Latch memory design with true and complementary outputs
10 Latch memory design with true and complementary outputs With active-high inputs Could be NOT gates but see later using NAND gates here S-R latch
11 Flip-Flops The latch design will store one binary value, but has the disadvantage that the outputs will change immediately one of the inputs changes to a 0. Often, we want the output changes to be synchronized with a clock signal. Such memory designs are usually called flip-flops. (Output flips to a 1, flops to a 0) There are several types of flip-flop.
12 S-R flip-flop (Clocked S-R latch) Essentially the same characteristics of the memory latch in that it has two inputs, named S for (set) and R for (reset). The S input when a 1 will set the output to a 1, while the R input when a 1 will reset the output to a 0. Synchronous operation requires an additional clock input and only after a specified clock transition occurs will the outputs take on the required values Before the clock transition occurs, the outputs will not change even if the S and R inputs change.
13 S-R flip-flop truth table Flip-Flop Truth Tables Flip-flops can be described by a truth table. Q + indicates the value of Q after the activating clock transition. Q - is sometimes used to indicate the value of Q before the activating clock transition. X indicates an undefined output.
14 Level triggering When the clock becomes a 1, the outputs assume their values according to S and R. Level triggered S-R flip-flop Clock Assumed that S and R will not change while clock at a 1.
15 Level triggered S-R flip flop timing
16 D-type flip-flop Stores one binary digits. The Q output simply becomes the value on the D input after the activating clock transition. Q + indicates the value of Q after the activating clock transition. Truth table of D-type flip-flop
17 Level triggered D latch design
18 Time of Output Change In positive edge triggering, the activating transition is from a logic 0 to a logic 1. In negative edge triggering, the activating transition is from a logic 1 to a logic 0. Both forms are common. Edge Triggered Designs (usual for flop –flops) The output changes on a transition of the clock signal (edge). The inputs are allowed to change at other times without affecting the output.
21 D-type flip-flop symbols with asynchronous set and reset inputs Positive edge triggered
22 Common requirements is to create a circuit whose outputs change from a 0 to a 1 or from a 1 to a 0, e.g. binary counter. J–K flip-flop provides this toggle operation in additional to being able to set the output to a 1 or reset the output to a 0. J–K flip-flop truth table Output toggles Same as S-R flip-flop Not allowed in S-R flip-flop
24 State Diagrams Sequential circuits exist in defined states, described in a state diagram. All practical sequential circuits have a finite number of states, hence the term finite state machine for describing practical sequential circuits. A flip-flip can exist in one of two states: 1. When the output is a 0, and 2. When the output is a 1. A state change initiated by a specified change of inputs and the activating clock transition (for “synchronous” sequential circuits having clock input).
25 D-type Flip Flop State Diagram (Moore model) A state diagram of a D-type flip-flop:
26 J-K Flip Flop State Diagram (Moore model) A state diagram of a J-K flip-flop:
27 Questions Next we will explore using flip-flops to create more complex sequential circuits