Presentation on theme: "Give qualifications of instructors: DAP"— Presentation transcript:
1ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Give qualifications of instructors:DAPteaching computer architecture at Berkeley since 1977Co-athor of textbook used in classBest known for being one of pioneers of RISCcurrently author of article on future of microprocessors in SciAm Sept 1995RYtook 152 as student, TAed 152,instructor in 152undergrad and grad work at Berkeleyjoined NextGen to design fact 80x86 microprocessorsone of architects of UltraSPARC fastest SPARC mper shipping this Fall
2Circuits require memory to store intermediate data OverviewCircuits require memory to store intermediate dataSequential circuits use a periodic signal to determine when to store values.A clock signal can determine storage timesClock signals are periodicSingle bit storage element is a flip flopA basic type of flip flop is a latchLatches are made from logic gatesNAND, NOR, AND, OR, Invertercredential:bring a computerdie photowafer:This can be an hidden slide. I just want to use this to do my own planning.I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but mayWe will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
3For example, can add two numbers. But: The story so far ...Logical operations which respond to combinations of inputs to produce an output.Call these combinational logic circuits.For example, can add two numbers. But:No way of adding two numbers, then adding a third (a sequential operation);No way of remembering or storing information after inputs have been removed.To handle this, we need sequential logic capable of storing intermediate (and final) results.
4Combinational circuit Sequential CircuitsCombinational circuitFlip FlopsOutputsInputsNext statePresent stateTiming signal (clock)Clocka periodic external event (input)synchronizes when current state changes happenkeeps system well-behavedmakes it easier to design and build large systems
5Cross-coupled Inverters A stable value can be stored at inverter outputsState 1State 2
6S-R latch made from cross-coupled NORs If Q = 1, set state S-R Latch with NORsR (reset)QS R Q Q’1 11 00 10 00 0 Undefined1 0 Set0 1 ResetQ0 1S (set)Stable1 0S-R latch made from cross-coupled NORsIf Q = 1, set stateIf Q = 0, reset stateUsually S=0 and R=0S=1 and R=1 generates unpredictable results
7Latch made from cross-coupled NANDs Sometimes called S’-R’ latch S-R Latch with NANDsS R Q Q’SRQQ’0 00 11 01 11 1 Disallowed1 0 Set0 1 Reset0 1Store1 0Latch made from cross-coupled NANDsSometimes called S’-R’ latchUsually S=1 and R=1S=0 and R=0 generates unpredictable results
9S-R Latch with control input Occasionally, desirable to avoid latch changesC = 0 disables all latch state changesControl signal enables data change when C = 1Right side of circuit same as ordinary S-R latch.
10NOR S-R Latch with Control Input Latch is level-sensitive, in regards to COnly stores data if C’ = 0R’QC’Q’Latch operation enabled byCS’Outputs change when C is low:RESET and SETOtherwise: HOLDInput sampling enabled by gates
11Q0 indicates the previous state (the previously stored value) D LatchQ0 indicates the previous state (the previously stored value)XSDQCQ’RYX Y C Q Q’Q0 Q0’ StoreResetSetDisallowedX X 0 Q0 Q0’ StoreX 0 Q0 Q0’D C Q Q’
12Input value D is passed to output Q when C is high D LatchXSDQCQ’RYX 0 Q0 Q0’D C Q Q’Input value D is passed to output Q when C is highInput value D is ignored when C is low
13Z only changes when E is high If E is high, Z will follow X D LatchLatches on followingedge of clockEEDQCxzxzZ only changes when E is highIf E is high, Z will follow X
14Forms basic storage element in computers D LatchLatches on followingedge of clockEEDQCxzxzThe D latch stores data indefinitely, regardless of input D values, if C = 0Forms basic storage element in computers
15Symbols for LatchesSR latch is based on NOR gatesS’R’ latch based on NAND gatesD latch can be based on either.D latch sometimes called transparent latch
16Latches are based on combinational gates (e.g. NAND, NOR) SummaryLatches are based on combinational gates (e.g. NAND, NOR)Latches store data even after data input has been removedS-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset)With additional gates, an S-R latch can be converted to a D latch (D stands for data)D latch is simple to understand conceptuallyWhen C = 1, data input D stored in latch and output as QWhen C = 0, data input D ignored and previous latch value output at QNext time: more storage elements!credential:bring a computerdie photowafer:This can be an hidden slide. I just want to use this to do my own planning.I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but mayWe will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.