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CHAPTER 7 Flip-Flops, Registers, Counters, and a Simple Processor.

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Presentation on theme: "CHAPTER 7 Flip-Flops, Registers, Counters, and a Simple Processor."— Presentation transcript:

1 CHAPTER 7 Flip-Flops, Registers, Counters, and a Simple Processor

2 Chapter Objectives  In this chapter you will learn about:  Logic circuits that can store information  Flip-flops, which store a single bit  Registers, which store multiple bits  Shift registers, which shift the contents of a register  Counters of various types  VHDL constructs used to implement storage elements  Design of small subsystems  Timing considerations

3 Memory element Alarm Sensor Reset Set OnOff  Motivation: Control of an Alarm System  Alarm turned on when On/Off = 1  Alarm turned off when On/Off = 0  Once triggered, alarm stays on until manually reset  The circuit requires a memory element

4 The Basic Latch  Basic latch is a feedback connection of two NOR gates or two NAND gates  It can store one bit of information  It can be set to 1 using the S input and reset to 0 using the R input.

5 AB A Simple Memory Element  A feedback loop with even number of inverters  If A = 0, B = 1 or when A = 1, B = 0  This circuit is not useful due to the lack of a mechanism for changing its state

6 Reset SetQ A Memory Element with NOR Gates

7 The Gated Latch  Gated latch is a basic latch that includes input gating and a control signal  The latch retains its existing state when the control input is equal to 0  Its state may be changed when the control signal is equal to 1. In our discussion we referred to the control input as the clock  We consider two types of gated latches:  Gated SR latch uses the S and R inputs to set the latch to 1 or reset it to 0, respectively.  Gated D latch uses the D input to force the latch into a state that has the same logic value as the D input.

8 Gated S/R Latch

9 Gated D Latch

10 t su t h Clk D Q Setup and Hold Times  Setup Time t su  The minimum time that the input signal must be stable prior to the edge of the clock signal.  Hold Time t h  The minimum time that the input signal must be stable after the edge of the clock signal.

11 Flip-Flops  A flip-flop is a storage element based on the gated latch principle  It can have its output state changed only on the edge of the controlling clock signal

12 Flip-Flops  We consider two types:  Edge-triggered flip-flop is affected only by the input values present when the active edge of the clock occurs  Master-slave flip-flop is built with two gated latches The master stage is active during half of the clock cycle, and the slave stage is active during the other half. The output value of the flip-flop changes on the edge of the clock that activates the transfer into the slave stage.

13 D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s D Q m QQ s = D Q Q (a) Circuit (b) Timing diagram (c) Graphical symbol Clk Master-Slave D Flip-Flop

14 D Q Q Graphical symbol Clock A Positive-Edge-Triggered D Flip-Flop

15 Comparison of Level-Sensitive and Edge- Triggered D Storage Elements

16 D Q Q Clear Preset Master-Slave D Flip-Flop with Clear and Preset

17 T Flip-Flop

18 JK Flip-Flop

19 Registers and Counters  An n-bit register is a cascade of n flip-flops and can store an n-bit binary data  A counter can count occurrences of events and can generate timing intervals for control purposes

20 A Simple Shift Register

21 Parallel-Access Shift Register Performs both as a series-to- parallel and a parallel-to- series converter

22 A Three-Bit Up-Counter  Q 1 is connected to clk, Q 2 and Q 3 are clocked by Q’ of the preceding stage (hence called asynchronous or ripple counter)

23 A Three-Bit Down-Counter  Q 1 is connected to clk, Q 2 and Q 3 are clocked by Q of the preceding stage (asynchronous or ripple counter)

24 Clock cycle 0080 Q 2 Q 1 Q 0 Q 1 changes Q 2 Derivation of the Synchronous Up- Counter  Q 0 changes with clk, Q 2 changes when previous state of Q 0 was 1, and Q 3 changes when previous state of Q 1 and Q 0 were 1

25 A Four-Bit Synchronous Up-Counter

26 T Q Q Clock T Q Q Enable Clear T Q Q T Q Q Inclusion of Enable and Clear Capability


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