1. Aug 23, ‘021Low-Power Design Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974 USA va@agere.com http://cm.bell-labs.com/cm/cs/who/va Bangalore, August 23, 2002 Research Collaborators: M. L. Bushnell, Rutgers University T. Raja, Rutgers University

2. Aug 23, ‘022Low-Power Design Power in a CMOS Gate VDD = 5V IDD Ground

3. Aug 23, ‘023Low-Power Design Motivation Low power applications Remote systems (e.g., satellite) Portable systems (e.g., mobile phone) Methods of low power design Reduced supply voltage Adiabatic switching Clock suppression Logic design for reduced activity Reduce Hazards (40% in arithmetic logic) Software techniques Reference: Chandrakasan and Brodersen

4. Aug 23, ‘024Low-Power Design Problem Statement Design a digital circuit for minimum transient energy consumption by eliminating hazards

5. Aug 23, ‘025Low-Power Design Main Result: Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition

6. Aug 23, ‘026Low-Power Design Given that events occur at the input of a gate (inertial delay = d ) at times t 1 <... < t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t 1 --------d t n - t 1 + d t n - t 1 + d t 1 t 2 t 3 t n t n + d t 1 t 2 t 3 t n t n + d time time

7. Aug 23, ‘027Low-Power Design Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

8. Aug 23, ‘028Low-Power Design Balanced Delay Method All input events arrive simultaneously Overall circuit delay not increased Delay buffers may have to be inserted 1 1 1 1 1 1 1 1 3 1 1 4?

9. Aug 23, ‘029Low-Power Design Hazard Filter Method Gate delay is made greater than maximum input path delay difference No delay buffers needed (least transient energy) Overall circuit delay may increase 2 1 1 1 1 2 1 1 1 1 1? 3?

10. Aug 23, ‘0210Low-Power Design Linear Program Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gates AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

11. Limitation of this LP Constraints are written by path enumeration. Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.

12. New linear programming model Introduce two new variables per gate output: t i Earliest time of signal transition at gate i. T i Latest time of signal transition at gate i. t 1, T 1 t n, T n...... t i, T i

13. Timing window Input signals transition within intervals [ t i, T i ] Output transition interval = [ t 1, T n +d ]

14. New linear program Gate variables d 4..d 12 Buffer Variables d 15..d 29 Corresponding window variables t 4..t 29 and T 4..T 29.

15. Gate constraints – multiple inputs For Gate 7: T 7 > T 5 + d 7 ;t 7 T 7 - t 7 ; T 7 > T 6 + d 7 ;t 7 < t 6 + d 7 ;

16. Gate constraints – single input T 16 + d 19 = T 19 ; t 16 + d 19 = t 19 ; Buffer 19:

17. Overall delay constraints T 11 < maxdelay T 12 < maxdelay

18. Validation of the model For Gate 6 (old model): d 1 + d 3 – d 2 < d 6 d 2 – d 3 – d 1 < d 6

19. Validation of the model For Gate 6 (new model): T 6 > T 2 + d 6 ; t 6 T 6 - t 6 ; T 6 > T 3 + d 6 ; t 6 < t 3 + d 6 ;.. (Ineq. set A)

20. Validation of the model Buffer Constraints: T 2 = t 2 = d 2 ; T 3 = t 3 = d 3 ; (Ineq. set B) Substituting Ineq. set B in Ineq. set A t 6 – d 2 < d 6..( 1 ) t 6 – d 1 – d 3 < d 6..( 2 ) d 6 < T 6 – d 2..( 3 ) d 6 < T 6 – d 1 – d 3..( 4 )

21. Validation of the model Adding inequalities ( 1 ) and ( 4 ) d 1 + d 3 – d 2 < T 6 – t 6 Adding inequalities ( 2 ) and ( 3 ) d 2 - d 3 – d 1 < T 6 – t 6 These are the same inequalities from the old model. Similar derivation can be done for maxdelay constraints too. Hence the new model constraints are equivalent to the old ones.

22. Why this model is superior? Path constraints from old model 4 × 4 × …4 = 4 n Constraints from new model 15 × n = 15n Hence new constraint set is linear in size of circuit.

23. Comparison of constraint sets Number of gates in circuit Number of constraints c880 3,611 6.96x10 6

24. Results: Procedure outline C++ Program AMPL Power Estimator Combinational circuit netlist Results Constraint-set Optimized delays

25. Results – 1 bit adder

26. Estimation of power Circuit is simulated by an event-driven simulator for both optimized and un- optimized gate delays. All transitions at a gate are counted as Events[gate]. Power consumed  Events[gate] x # of fanouts. Reference: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ISLPED`97).

27. 1-bit Adder: Transitions Number of transitions Vector-pair in octal 01 07 17 27 37 47 57 67 77 15 10 5 0 Avg =5.10 Avg =4.01 Unit-delays Optimized delays

28. Results: 1-bit adder Color codes for number of transitions

29. Results: 1-bit adder Color codes for number of transitions

30. Results: 1-bit adder Simulated over all possible vector transitions Average power = optimized/unit delay = 244 / 308 = 0.792 Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 %

31. Results: 4-bit ALU maxdelayBuffers inserted 75 102 121 150 Simulation with 1,000 random vectors: Average power = optimized/unit delay = 2431 / 3060 = 0.794 Peak power = optimized/unit delay = 28 / 42 = 0.66 Power Savings : Peak = 33 %, Average = 21 %

32. Conclusion Obtained an LP constraint-set that is linear in the size of the circuit. LP solution: Eliminates glitches at all gate outputs, Holds I/O delay within specification, and Combines path-balancing and hazard-filtering to minimize the number of delay buffers. New LP produces results exactly identical to old LP requiring exponential constraint-set. Results show peak power savings up to 40% and average power savings up to 21%.