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Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.

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Presentation on theme: "Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE."— Presentation transcript:

1 Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE Dept., Auburn, Alabama, USA PATMOS’05, Leuven, Belgium, September 21-23, 2005

2 2 Problem Statement  Design a CMOS Circuit :  with dual-threshold devices to globally minimize subthreshold leakage  with delay elements to eliminate all glitches  to maintain specified performance  Allow Performance-Power tradeoff

3 3 CLCL Dynamic Switching Power + Short Circuit Power + Leakage Power Power Consumption in CMOS Circuits

4 4 Leakage and Delay  Increasing V th can exponentially decrease I sub  But, gate delay increases at the same time where α models channel effects (long channel α = 2, short channel α = 1.3)  While using dual V th techniques, must consider the tradeoff between leakage reduction and performance degradation

5 5 Some Previous References on Leakage Reduction and Glitch Power Reduction  Leakage Power Minimization by Dual-V th CMOS Devices  Heuristic Algorithms (locally optimal solution)  Q. Wang and S. B. K. Vrudhula, "Static Power Optimization of Deep Submicron CMOS Circuits for Dual V T Technology," Proc. ICCAD, 1998, pp  L. Wei, Z. Chen, M. Johnson and K. Roy, “Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits,” Proc. DAC, 1998, pp  Linear Programming (globally optimum solutions)  D. Nguyen, A. Davare, M. Orshansky, D. Chinney, B. Thompson and K. Keutzer, “Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization,” Proc. ISLPED, 2003, pp  F. Gao and J. P. Hayes, “Gate Sizing and V t Assignment for Active-Mode Leakage Power Reduction,” Proc. ICCD, 2004, pp  Dynamic Glitch Power Elimination by Linear Programming  T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16th International Conference on VLSI Design, 2003, pp

6 6 New MIP : A Mixed Integer Linear Program for Leakage and Glitch Power Reduction  Objective Function: Minimize {Total leakage + No. of glitch suppressing delay elements}  Alternative objective function (linear approximation): Minimize {Total leakage + Total glitch suppressing delay}

7 7 Objective Function Minimize { Σ X i I Li + (1-X i )I Hi all gates i + Σ Σ Δd ij } all gates i→ j WhereX i = 1, gate i has low V th, leakage = I Li X i = 0, gate i has high V th, leakage = I Hi Δd ij = delay inserted between gates i and j for glitch suppression X i = [0,1] is integer, Δd ij is real variable I Li and I Hi are constants for gate i determined by SPICE

8 8 MIP: Variables and Constants Each gate has four variables and four constants: Integer Variable:  X i :[0,1], specifies gate threshold voltage Continuous-valued Variales:  T i :latest time at which the output of gate i can produce an event after the occurrence of an event at primary inputs.  t i :earliest time at which the output of gate i can produce an event after the occurrence of an event at primary inputs.  Δd i,j : delay of inserted delay element at the j th input of gate i. Constants Determined by Spice Simulation  I Li and I Hi :Leakage currents for low and high thresholds  D Li and D Hi : Delays for low and high thresholds

9 9 MIP - Constraints  Circuit delay constraint for each PO i:  T max can the delay of critical path or clock period specified by the circuit designer  Glitch suppression constraint for each gate i:  Constraints (g-2,3,4) make sure that T i - t i < d i for each gate, so glitches are eliminated

10 10 MIP - gate constraints explained  Constraints 1 & 2 let T 2 be the largest arrival time at gate 2 output  Constraints 3 & 4 let t 2 be the earliest arrival time at gate 2 output  Constraint 5 makes sure that T 2 - t 2 < d 2  D 2 can be a larger delay (high V th ) or a smaller delay (low V th ) (t 2, T 2 ) (t0,T0)(t0,T0) (1) (2) (3) (4) (5)

11 11 Power-Delay Tradeoff Example A 14-Gate Full Adder Unoptimized CircuitOptimized T max =T c Optimized T max =1.25 T c

12 12 Choices for a Delay Element  Two cascaded-inverter buffer - consumes additional subthreshold leakage and dynamic power:  All delay buffers are on non-critical paths and are assigned high V th, to reduce leakage overhead  Transmission gate (on state) – increases resistance  Smaller area overhead  No subthreshold leakage  Possible capacitance increase  Used before  T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” Proc. 18th International Conference on VLSI Design, January 2005, pp  T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits,” PATMOS’05.

13 13 Delay Element Implementation (a) Transmission Gate (b) Buffer Delay Element Subthreshold Leakage (pA) Transmission Gate High V th 0 Low V th 0 Buffer (Two Cascaded Inverters) High V th 409 Low V th * size of buffer: W/L:N1:315/70 P1:630/70 N2:175/70 P2:350/70

14 14 Leakage reduction and performance tradeoff 27 ℃, 70nm Circuit Number of gates Critical Path Delay T c (ns) Unoptimized I leak (μA) Optimized I leak (μA) (T max = T c ) Leakage Red. % Sun OS 5.7 CPU secs. Optimized for I leak (μA) (T max =1.25T c ) Leakage Red. % Sun OS 5.7 CPU secs. C C C C C C C C C C

15 15 Leakage Reduction and Performance  As we allow increase of T max from the smallest value T c, more leakage power can be saved, because more gates can be assigned high V th.  But, the trend slows down.  When T max ≈ 1.3 T c, the reduction trend saturates, because almost all gates have been assigned high V th, and there is no more optimization space left.  The maximum leakage reduction can be 98%.

16 16 Comparing Dynamic & Leakage Power  Leakage (increases with temperature):  Determined by Spice simulation of gates at 90 º C  Added up for all gates of circuit optimized by MIP  Dynamic power (depends on node activity and capacitance):  Node capacitances for optimized circuit estimated  Gate delays determined by Spice simulation of gates  Activity determined by event driven discrete-time simulator using 1,000 random vectors applied with 120% T c clock period

17 17 Leakage, Dynamic and Total Power Comparison 90 ℃, 70nm Circuit Name No. of Gates Leakage PowerDynamic PowerTotal Power P leak 1 (uW) P leak 2 (uW) Leakage Reduction P dyn 1 (uW) P dyn 2 (uW) Dynamic Reduction P total 1 (uW) P total 2 (uW) Total Reduction C % % % C % % % C % % % C % % % C % % % C % % % C % % % C % % % C % % % C % % %

18 18 Conclusion  A new mixed integer linear programming technique  Simultaneous minimization of leakage (dual-V th ) and elimination of glitches (path delay balancing)  Global tradeoff between power and performance  Experimental results shows that 96%, 40% and 70% reduction in leakage, dynamic (glitch) and total power, respectively.  Future directions:  Include gate sizing for switching capacitance reduction and leakage reduction  Allow dual-supply voltages for reduction of power components  Robust optimization for process variations

19 Thank You All ! Questions?


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