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1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL 36849 Hillary Grimes & Vishwani D. Agrawal.

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Presentation on theme: "1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL 36849 Hillary Grimes & Vishwani D. Agrawal."— Presentation transcript:

1 1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL Hillary Grimes & Vishwani D. Agrawal

2 2 Outline Problem Statement Reconvergent Fanout Analysis  Ambiguity Lists Fault Detection  Detection Threshold  Detection Gap Results Conclusion

3 3 Definitions Gate Delay Fault Model  Assume that a delay fault is lumped at a single faulty gate Detection Threshold  Minimum size delay fault that is guaranteed to be detected by the test Detection Gap  Relates the detection threshold to the slack at the fault site

4 4 Problem Statement When signals produced by a common fanout point reconverge, the inputs to the reconvergent gate are correlated Conventional simulation ignores this correlation when bounded gate delays are used  Produces pessimistic results in both bounded delay simulation and gate delay fault simulation

5 5 Bounded Delay Simulation 1,3 1,2 3,

6 6 Reconvergent Fanout Analysis 1,3 1,2 3,4 1 x Fall occurs at time ‘x’ x+1 5 Output rises at least 1 unit after ‘x’ Hazard cannot occur 0 1 1

7 7 Ambiguity Lists Ambiguity Lists generated at fanout points contain  originating fanout name  ambiguity interval – min and max delays from fanout to gate Ambiguity list propagation is similar to fault list propagation in concurrent fault simulation

8 10/25/2007 ITC-07 Paper Ambiguity List Propagation Ambiguity lists at the inputs of a reconvergent gate help determine its output  If signal correlations are such that no hazard can occur, the hazard is suppressed  Otherwise, the ambiguity lists are propagated to the gate’s output, and ambiguity intervals are updated

9 10/25/2007 ITC-07 Paper Ambiguity List Propagation Bounded Delay Simulation  Ambiguity lists propagated through every gate Detection Threshold Evaluation  Ambiguity Lists propagated through downcone of the fault site

10 10 Detection Threshold 1,3 1,2 3, Corrected Det. Threshold = 6 Ts = 12 Det. Threshold = 8

11 11 Detection Gap for a Gate Ideal gate delay test should activate longest path p1, detection threshold = slack, gap = 0 A test that activates path p2, p2 < p1, gap = detection threshold – slack Smaller the gap, better is the test PI PO p1 - longest delay path through gate p2 Gate Ts p1 delay p2 delay gap DT(p2) slack t

12 12 Results ISCAS85 benchmark circuits simulated with 10,000 random vectors Simple wireload model  Bounded delays set to (3.5n ± 14%), where n is the number of fanouts  Program can accept any available gate delay data, which may be normally available from process technology characterization

13 13 Results: Fault-Free Simulation Circuit Without Reconvergent Fanout Analysis With Reconvergent Fanout Analysis Largest EALargest LSLargest EALargest LS c C C C Using reconvergent fanout analysis generally results in larger EA and smaller LS values at outputs More apparent for circuits that contain a large number of reconvergent fanouts, such as in multiplier circuit c6288

14 14 Results: Fault Simulation Average detection gap and fault coverage of faults detected with gap ≤ 3.5 recorded For fault coverage, faults are counted as detected if they are detected:  Through the longest path through the gate  Through a path which is shorter than longest path by only one gate delay

15 15 Results: Fault Simulation Circuit Without Reconvergent Fanout Analysis With Reconvergent Fanout Analysis Average Detection Gap Faults Detected with Gap ≤ 3.5 Average Detection Gap Faults Detected with Gap ≤ 3.5 c % % c % % c % % c % % c % % c % % c % % c % % c % %

16 16 Conclusion When reconvergent fanout analysis is used, gate delay fault simulation results are less pessimistic During simulation, ambiguity lists can grow quite large  Efficiency in list propagation needs to be improved This min-max delay simulator has found application in hazard-free delay test generation


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