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Low Power Design of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor ECE Dept., Auburn University, Auburn, AL 36849 Nov 19, 20091Agrawal: Low.

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Presentation on theme: "Low Power Design of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor ECE Dept., Auburn University, Auburn, AL 36849 Nov 19, 20091Agrawal: Low."— Presentation transcript:

1 Low Power Design of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor ECE Dept., Auburn University, Auburn, AL Nov 19, 20091Agrawal: Low Power Design

2 CMOS Logic (Inverter) F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid- State Circuits Conference Digest, vol. IV, February 1963, pp No static leakage path exists for either 1 or 0 input. Nov 19, 20092Agrawal: Low Power Design

3 Power of a CMOS Gate Transition V DD Ground CLCL R R Dynamic Power = C L V DD 2 /2 + P sc Static power = V DD I leakage ViVi VoVo i sc Nov 19, 20093Agrawal: Low Power Design

4 Power Consumption of VLSI Chips Why is it a concern? Nov 19, 20094Agrawal: Low Power Design

5 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP. Nov 19, 20095Agrawal: Low Power Design

6 VLSI Chip Power Density Pentium® P Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel  Nov 19, 20096Agrawal: Low Power Design

7 Low-Power Design Design practices that reduce power consumption by at least one order of magnitude; in practice 50% reduction is often acceptable. Low-power design methods: – Algorithms and architectures – High-level and software techniques – Gate and circuit-level methods – Test power Nov 19, 20097Agrawal: Low Power Design

8 Components of Power Dynamic – Signal transitions Logic activity Glitches – Short-circuit Static – Leakage P total =P dyn + P stat =P tran + P sc + P stat Then =P tran + P sc + P stat Now Nov 19, 20098Agrawal: Low Power Design

9 Dynamic Power Each transition of a gate consumes CV 2 /2. Methods of power saving: – Minimize load capacitances Transistor sizing – Reduce transitions Logic design Glitch reduction Nov 19, 20099Agrawal: Low Power Design

10 Glitch Power Reduction Design a digital circuit for minimum transient energy consumption by eliminating hazards Nov 19, Agrawal: Low Power Design Total transitions = 6 Essential transitions = 2 Glitch transitions = 4

11 Multi-Input Gate Delay D < DPD ABAB C ABCABC D DHazard or glitch DPD DPD: Differential path delay Nov 19, Agrawal: Low Power Design time

12 Balanced Path Delays Delay D < DPD ABAB C ABCABC D No glitch DPD Delay buffer Nov 19, Agrawal: Low Power Design time

13 Glitch Filtering by Inertia Delay D > DPD ABAB C ABCABC Filtered glitch DPD Nov 19, Agrawal: Low Power Design time

14 Designing a Glitch-Free Circuit Maintain specified critical path delay. Glitch suppressed at all gates by – Path delay balancing – Glitch filtering by increasing inertial delay of gates or by inserting delay buffers when necessary. A linear program optimally combines all objectives. Delay D Path delay = d1 Path delay = d2 Minimum transient energy condition: |d1 – d2| < D Nov 19, Agrawal: Low Power Design

15 Linear Program (LP) Variables: gate and buffer delays, arrival time variables. Objective: minimize number of delay buffers. Subject to: overall circuit delay constraint for all input-output paths. Subject to: minimum transient energy condition for all multi-input gates. Nov 19, Agrawal: Low Power Design

16 An Example: Full Adder 1 1 Critical path delay = Nov 19, Agrawal: Low Power Design

17 LP Step 1: Define Varaibles Gate delay variables:d 4... d 12 Buffer delay variables:d d 29 Arrival time variables (earliest):t 4... T 29 (longest):T T 29 Nov 19, Agrawal: Low Power Design

18 LP Step 2: Specify Constraints For Gate 7: T 7 ≥ T 5 + d 7 t 7 ≤ t 5 + d 7 d 7 > T 7 - t 7 T 7 ≥ T 6 + d 7 t 7 ≤ t 6 + d 7 Nov 19, Agrawal: Low Power Design

19 LP Step 2 (Cont.) T 16 + d 19 = T 19 t 16 + d 19 = t 19 Buffer 19: Nov 19, Agrawal: Low Power Design

20 LP Step 2: Critical Path Constraints T 11 ≤ maxdelay T 12 ≤ maxdelay maxdelay is specified Nov 19, Agrawal: Low Power Design

21 LP Step 3: Define Objective Function Need to minimize the number of buffers. Because that leads to a nonlinear objective function, we use an approximate criterion: minimize ∑ (all buffer delays) i.e.,minimize d 15 + d 16 + ∙ ∙ ∙ + d 29 This gives near optimum results. Nov 19, Agrawal: Low Power Design

22 LP Solution: maxdelay = Critical path delay = Nov 19, Agrawal: Low Power Design

23 LP Solution: maxdelay = Critical path delay = Nov 19, Agrawal: Low Power Design

24 LP Solution: maxdelay ≥ Critical path delay = Nov 19, Agrawal: Low Power Design

25 ALU4: Original and Glitch-Free Nov 19, Agrawal: Low Power Design

26 C7552 Circuit: Spice Simulation Power Saving: Average 58%, Peak 68% Nov 19, Agrawal: Low Power Design

27 Components of Power Dynamic – Signal transitions Logic activity Glitches – Short-circuit Static – Leakage Nov 19, Agrawal: Low Power Design

28 Leakage Reduction Problem 65nm CMOS technology: Low threshold transistors, gate delay 5ps, leakage current 10nA. High threshold transistors, gate delay 12ps, leakage 1nA. Minimize leakage current without increasing critical path delay. What is the percentage reduction in leakage power? What will be leakage power reduction if 30% critical path delay increase is allowed? Nov 19, Agrawal: Low Power Design

29 Solution 1: No Delay Increase Reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73% Critical path delay = 25ps 5ps 12ps Nov 19, Agrawal: Low Power Design

30 Solution 2: 30% Delay Increase Several solutions are possible. Notice that any 3-gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow. Reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09% Critical path delay = 29ps 12ps 5ps Nov 19, Agrawal: Low Power Design

31 Integer Linear Programming (ILP) to Minimize Leakage Power Assign every gate i an integer [0,1] variable Xi. Define ILP constraints and objective function: On critical path delay Minimize total leakage Let ILP find values of Xi’s: If Xi = 1, assign low threshold to gate i If Xi = 0, assign high threshold to gate i Nov 19, Agrawal: Low Power Design

32 Power-Delay Tradeoff Nov 19, Agrawal: Low Power Design

33 Leakage & Dynamic Power Optimization 70nm CMOS c7552 Benchmark 90 o C Leakage exceeds dynamic power Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power- Performance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp , December Nov 19, Agrawal: Low Power Design

34 Power Constrained Test Scheduling R1R2 M1 M2 R3R4 A datapath Nov 19, Agrawal: Low Power Design

35 Minimum Test Time LFSR1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2 Nov 19, Agrawal: Low Power Design

36 Minimum Test Power R1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2 Nov 19, Agrawal: Low Power Design

37 Testing of MCM and SOC Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR). Test resources (R1,...) and tests (T1,...) are identified for the system to be tested. Each test is characterized for test time, power dissipation and resources it requires. Nov 19, Agrawal: Low Power Design

38 Resource Allocation Graph (A Bipartite Graph) T1T2T3T4T5T6 R2R1R3R4R5R6R7R8R9 Nov 19, Agrawal: Low Power Design

39 Test Compatibility Graph (TCG) T1 (2, 100) T2 (1,10) T3 (1, 10) T4 (1, 5) T5 (2, 10) T6 (1, 100) Tests that form a clique can be performed concurrently. Power Test time Pmax = 4 Nov 19, Agrawal: Low Power Design

40 Find All Cliques in TCG CLIQUE NO. iTEST NODES TEST LENGTH, LiPOWER, Pi 1T1, T3, T T1, T3, T T1, T T1, T T1, T T1. T T2, T T2, T T3, T T3, T T T T T451 15T T61001 Nov 19, Agrawal: Low Power Design

41 Integer Linear Program (ILP) For each clique (test session) i, define: – Integer variable, xi = 1, test session selected, or xi = 0, test session not selected. – Constants, Li = test length, Pi = power. Constraints to cover all tests: – T1 is covered if x1+x2+x3+x4+x5+x6+x11 ≥ 1 – Similar constraint for each test, Tk Constraints for power: Pi × xi ≤ Pmax Nov 19, Agrawal: Low Power Design

42 ILP Objective and Solution Objective function: – Minimize Σ Li × xi all cliques Solution: – x3 = x8 = x10 = 1, all other xi’s are 0 Test session 3 includes T1 and T6 Test session 8 includes T2 and T5 Test session 10 includes T3 and T4 – Test length = L3 + L8 + L10 = 120 – Peak power = max {P3, P8, P10} = 3 (Pmax = 4) Nov 19, Agrawal: Low Power Design

43 Summary Underlying theme in our research – use of mathematical optimization methods for power reduction at gate level: Dynamic power Leakage power Power minimization under process variation Test power Other research Min-max power estimation Architecture level power management Nov 19, 2009Agrawal: Low Power Design43

44 Our Research Students T. Raja, MS 2002, PhD 2004 (NVIDIA) S. Uppalapati, MS 2004 (Intel) F. Hu, PhD 2006 (Intel) Y. Lu, PhD 2007 (Intel) J. D. Alexander, MS 2008 K. Sheth, MS 2008 M. Allani, PhD J. Yao, PhD K. Kim, PhD M. Kulkarni, MS Nov 19, Agrawal: Low Power Design

45 Dissertations and Papers Dissertations: Papers: Nov 19, 2009Agrawal: Low Power Design45


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