1. 9/23-30/04ELEC 5970-003/6970-0031 ELEC 5970-003/6970-003 (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Power Consumption in a CMOS Circuit Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 9/23-30/04ELEC 5970-003/6970-0032 Motivation Low power applications – Remote systems (e.g., satellite) – Portable systems (e.g., mobile phone) Methods of low power design – Reduced supply voltage – Adiabatic switching – Clock suppression – Logic design for reduced activity – Reduce Hazards (40% in arithmetic logic) – Software techniques Reference: Chandrakasan and Brodersen

3. 9/23-30/04ELEC 5970-003/6970-0033 Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. General topics –High-level and software techniques –Gate and circuit-level methods –Power estimation techniques –Test power

4. 9/23-30/04ELEC 5970-003/6970-0034 VLSI Chip Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

5. 9/23-30/04ELEC 5970-003/6970-0035 Specific Topics on Low-Power Power dissipation in CMOS circuits Low-power CMOS technologies Dynamic reduction techniques Leakage power Power estimation

6. 9/23-30/04ELEC 5970-003/6970-0036 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage

7. 9/23-30/04ELEC 5970-003/6970-0037 Power of a Transition V DD Ground CLCL R R Power = C L V DD 2 /2 + P sc ViVi VoVo i sc

8. 9/23-30/04ELEC 5970-003/6970-0038 Short Circuit Current, i sc (t) Time (ns) 0 1 Amp Volt V DD i sc (t) 45μA 0 V i (t) V o (t) V DD - V Tp V Tn tBtB tEtE I scmaxr

9. 9/23-30/04ELEC 5970-003/6970-0039 Peak Short Circuit Current Increases with the size (or gain, β) of transistors Decreases with load capacitance, C L Largest when C L = 0 Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS’96, Aug. 1996, pp. 147-166.

10. 9/23-30/04ELEC 5970-003/6970-00310 Short-Circuit Energy per Transition E scr = ∫ t B t E V DD i sc (t)dt = (t E – t B ) I scmaxr V DD /2 E scr = t r (V DD + V Tp -V Tn ) I scmaxr /2 E scf = t f (V DD + V Tp -V Tn ) I scmaxf /2 E scf = 0, when V DD = |V Tp | + V Tn

11. 9/23-30/04ELEC 5970-003/6970-00311 Short-Circuit Energy Increases with rise and fall times of input Decreases for larger output load capacitance Decreases and eventually becomes zero when V DD is scaled down but the threshold voltages are not scaled down

12. 9/23-30/04ELEC 5970-003/6970-00312 Short-Circuit Power Calculation Assume equal rise and fall times Model input-output capacitive coupling (Miller capacitance) Use a spice model for transistors –T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594.

13. 9/23-30/04ELEC 5970-003/6970-00313 P sc vs. C C (fF) Input rise time 3ns 0% 45% 0.5ns P sc /P total 0.7μ CMOS 3575

14. 9/23-30/04ELEC 5970-003/6970-00314 Technology Scaling Scale down by factors of 2 and 4, i.e., model 0.7, 0.35 and 0.17 micron technologies Constant electric field assumed Capacitance scaled down by the technology scale down factor

15. 9/23-30/04ELEC 5970-003/6970-00315 Technology Scaling Results t r (ns) 0% 70% P sc /P total L=0.7μ, C=40fF 0.41.6 10% L=0.35μ, C=20fF L=0.17μ, C=10fF

16. 9/23-30/04ELEC 5970-003/6970-00316 Effects of Scaling Down 1-16% short-circuit power at 0.7 micron 4-37% at 0.35 micron 12-60% at 0.17 micron Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp. 762-765.

17. 9/23-30/04ELEC 5970-003/6970-00317 Summary: Short-Circuit Power Short-circuit power is consumed by each transition (increases with input transition time). Reduction requires that gate output transition should not be slower than the input transition (faster gates can consume more short-circuit power). Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power.

18. 9/23-30/04ELEC 5970-003/6970-00318 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage

19. 9/23-30/04ELEC 5970-003/6970-00319 Leakage Power IGIG IDID I sub I PT I GIDL n+ Ground V DD R

20. 9/23-30/04ELEC 5970-003/6970-00320 Leakage Current Components Subthreshold conduction, I sub Reverse bias pn junction conduction, I D Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Drain source punchthrough, I PT due to short channel and high drain-source voltage Gate tunneling, I G through thin oxide

21. 9/23-30/04ELEC 5970-003/6970-00321 Subthreshold Current I sub = μ 0 C ox (W/L) V t 2 exp{(V GS -V TH )/nV t } μ 0 : carrier surface mobility C ox : gate oxide capacitance per unit area L: channel length W: gate width V t = kT/q: thermal voltage n: a technology parameter

22. 9/23-30/04ELEC 5970-003/6970-00322 I DS for Short Channel Device I sub = μ 0 C ox (W/L) V t 2 exp{(V GS -V TH +ηV DS )/nV t } V DS = drain to source voltage η: a proportionality factor

23. 9/23-30/04ELEC 5970-003/6970-00323 Increased Subthreshold Leakage 0V TH ’V TH Log I sub Gate voltage Scaled device IcIc

24. 9/23-30/04ELEC 5970-003/6970-00324 Summary: Leakage Power Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. For a gate it is a small fraction of the total power; it can be significant for very large circuits. Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. Multiple-threshold devices are used to reduce leakage power.

25. 9/23-30/04ELEC 5970-003/6970-00325 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage

26. 9/23-30/04ELEC 5970-003/6970-00326 Power of a Transition V DD Ground CLCL R R Power = C L V DD 2 /2 + P sc ViVi VoVo i sc

27. 9/23-30/04ELEC 5970-003/6970-00327 Dynamic Power Each transition of a gate consumes CV 2 /2. Methods of power saving: –Minimize load capacitances Transistor sizing Library-based gate selection –Reduce transitions Logic design Glitch reduction

28. 9/23-30/04ELEC 5970-003/6970-00328 Glitch Power Reduction Design a digital circuit for minimum transient energy consumption by eliminating hazards

29. 9/23-30/04ELEC 5970-003/6970-00329 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition

30. 9/23-30/04ELEC 5970-003/6970-00330 Given that events occur at the input of a gate (inertial delay = d ) at times t 1 <... < t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t 1 --------d t n - t 1 t n - t 1 t 1 t 2 t 3 t n t 1 t 2 t 3 t n time time

31. 9/23-30/04ELEC 5970-003/6970-00331 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

32. 9/23-30/04ELEC 5970-003/6970-00332 Balanced Delay Method All input events arrive simultaneously Overall circuit delay not increased Delay buffers may have to be inserted 1 1 1 1 1 1 1 1 3 1 1 4?

33. 9/23-30/04ELEC 5970-003/6970-00333 Hazard Filter Method Gate delay is made greater than maximum input path delay difference No delay buffers needed (least transient energy) Overall circuit delay may increase 2 1 1 1 1 2 1 1 1 1 1? 3?

34. 9/23-30/04ELEC 5970-003/6970-00334 Linear Program Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gates AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

35. 9/23-30/04ELEC 5970-003/6970-00335 Variables: Full Adder add1b 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

36. 9/23-30/04ELEC 5970-003/6970-00336 Objective Function Ideal: minimize the number of non-zero delay buffers Actual: sum of buffer delays

37. 9/23-30/04ELEC 5970-003/6970-00337 Specify Critical Path Delay 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Sum of delays on critical path ≤ maxdel

38. 9/23-30/04ELEC 5970-003/6970-00338 Multi-Input Gate Condition 1 1 1 1 0 0 0 0 0 0 d1 d2 d d1 - d2 ≤ d d2 - d1 ≤ d d d

39. 9/23-30/04ELEC 5970-003/6970-00339 AMPL Solution: maxdel = 6 2 1 1 1 1 1 2 1 2 2 1

40. 9/23-30/04ELEC 5970-003/6970-00340 AMPL Solution: maxdel = 7 2 2 1 1 1 1 1 1 3 2

41. 9/23-30/04ELEC 5970-003/6970-00341 AMPL Solution: maxdel ≥ 11 2 3 1 1 1 1 4 3 5

42. 9/23-30/04ELEC 5970-003/6970-00342 Power Estimates for add1b maxdel No.ofbuf. Power* with respect to Ref. Ref: model del. Ref: unit del. PeakAve.PeakAve. 67≥11 2100.600.560.520.890.850.800.600.560.520.900.860.81 * Hsiao et al., ICCAD-97

43. 9/23-30/04ELEC 5970-003/6970-00343 Power Calculation in Spice VDD Ground Circuit Large C Open at t = 0 Ref.: M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, p. 172. t Energy, E(t) E(t) = -- C VDD 2 - -- C V 2 ~ C VDD ( VDD - V ) 11 22 V

44. 9/23-30/04ELEC 5970-003/6970-00344 Power Dissipation of ALU4 Energy in nanojoules 0 1 2 3 4 5 6 7 0.00.5 1.0 1.5 2.0 microseconds Original ALU delay ~ 3.5ns Minimum energy ALU delay ~ 10ns 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice

45. 9/23-30/04ELEC 5970-003/6970-00345 F0 Output of ALU4 Signal Amplitude, Volts 0 5 040 80 120 160 nanoseconds Original ALU, delay = 7 units (~3.5ns) Minimum energy ALU, delay = 21 units (~10ns) 5 0

46. 9/23-30/04ELEC 5970-003/6970-00346 References E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Nov. 1996, pp. 183-188; also Int. Workshop on Logic Synthesis, May 1997. V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 434-439. Last two papers are available at website http://www.eng.auburn.edu/~vagrawal http://www.eng.auburn.edu/~vagrawal

47. 9/23-30/04ELEC 5970-003/6970-00347 A Limitation Constraints are written by path enumeration. Since number of paths in a circuit can be exponential in circuit size, the formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.

48. 9/23-30/04ELEC 5970-003/6970-00348 Timing Window Define two timing window variables per gate output: –t i Earliest time of signal transition at gate i. –T i Latest time of signal transition at gate i. t 1, T 1 t n, T n...... t i, T i Ref: T. Raja, Master’s Thesis, Rutgers Univ., 2002 i

49. 9/23-30/04ELEC 5970-003/6970-00349 Linear Program Gate variables d 4... d 12 Buffer Variables d 15... d 29 Corresponding window variables t 4... t 29 and T 4... T 29.

50. 9/23-30/04ELEC 5970-003/6970-00350 Multiple-Input Gate Constraints For Gate 7: T 7 > T 5 + d 7 ; t 7 T 7 - t 7 ; T 7 > T 6 + d 7 ; t 7 < t 6 + d 7 ;

51. 9/23-30/04ELEC 5970-003/6970-00351 Single-Input Gate Constraints T 16 + d 19 = T 19 ; t 16 + d 19 = t 19 ; Buffer 19:

52. 9/23-30/04ELEC 5970-003/6970-00352 Overall Delay Constraints T 11 < maxdelay T 12 < maxdelay

53. 9/23-30/04ELEC 5970-003/6970-00353 Advantage of Timing Window Path constraints (exponential in n): 2 × 2 × … 2 = 2 n paths between I/O pair A single variable specifies I/O delay. Total variables, O(n). LP constraint set is linear in the size of circuit.

54. 9/23-30/04ELEC 5970-003/6970-00354 Comparison of Constraints Number of gates in circuit Number of constraints

55. 9/23-30/04ELEC 5970-003/6970-00355 Results: 1-Bit Adder

56. 9/23-30/04ELEC 5970-003/6970-00356 Estimation of Power Circuit is simulated by an event-driven simulator for both optimized and un- optimized gate delays. All transitions at a gate are counted as Events[gate]. Power consumed  Events[gate] x # of fanouts. Ref: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ICCAD`97).

57. 9/23-30/04ELEC 5970-003/6970-00357 Original 1-Bit Adder Color codes for number of transitions

58. 9/23-30/04ELEC 5970-003/6970-00358 Optimized 1-Bit Adder Color codes for number of transitions

59. 9/23-30/04ELEC 5970-003/6970-00359 Results: 1-Bit Adder Simulated over all possible vector transitions Average power = optimized/unit delay = 244 / 308 = 0.792 Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 %

60. 9/23-30/04ELEC 5970-003/6970-00360 Results: 4-Bit ALU maxdelayBuffers inserted 75 102 121 150 Power Savings : Peak = 33 %, Average = 21 %

61. 9/23-30/04ELEC 5970-003/6970-00361 Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) 17 34 24 48 47 94 43 86 No. of Buffers 95 66 62 34 294 120 366 111 Average 0.72 0.62 0.68 0.40 0.36 0.38 0.36 Peak 0.67 0.60 0.54 0.52 0.36 0.34 0.32 Normalized Power

62. 9/23-30/04ELEC 5970-003/6970-00362 Physical Design Gate l/w Gate l/w Gate l/w Gate l/w Gate delay modeled as a linear function of gate size, total load capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996). Layout circuit with some nominal gate sizes. Enter extracted routing delays in LP as constants and solve for gate delays. Change gate sizes as determined from a linear system of equations. Iterate if routing delays change.

63. 9/23-30/04ELEC 5970-003/6970-00363 Power Dissipation of ALU4

64. 9/23-30/04ELEC 5970-003/6970-00364 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993. M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183-188. V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10 th Int’l Conf. VLSI Design, Jan. 1997, pp. 193-197. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12 th Int’l Conf. VLSI Design, Jan. 1999, pp. 434-439. M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51. T. Raja, A Reduced Constraint Set Linear Program for Low Power Design of Digital Circuits, Master’s Thesis, Rutgers Univ., New Jersey, 2002.

65. 9/23-30/04ELEC 5970-003/6970-00365 Conclusion Glitch-free design through LP: constraint-set is linear in the size of the circuit. LP solution: –Eliminates glitches at all gate outputs, –Holds I/O delay within specification, and –Combines path-balancing and hazard-filtering to minimize the number of delay buffers. Linear constraint set LP produces results exactly identical to the LP requiring exponential constraint-set. Results show peak power savings up to 68% and average power savings up to 64%.