Download presentation

Presentation is loading. Please wait.

Published byKelsi Jean Modified over 2 years ago

1
CS370 – Spring 2003 Hazards/Glitches

2
Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them Chapter Overview

3
Timing behavior of circuits is emphasized waveforms are useful to visualize what is happening Logic simulation can be used to create these waveforms Hazards : momentary change of signals at the outputs can be useful -- pulse shaping circuits can be a problem -- glitches: incorrect circuit operation Terms: gate delay -- time for change at input to cause change at output. rise time -- time for output to transition from low to high voltage fall time -- time for output to transition from high to low voltage Time Response in Combinational Networks

4
Pulse Shaping Circuit A' A = 0 F is not always 0! 3 gate delays D remains high for three gate delays after A changes from low to high Time Response in Combinational Networks A B F C D

5
Another Pulse Shaping Circuit Initially undefined Close Switch Open Switch + AB CD Open Switch Resistor

6
Hazards/Glitches and How to Avoid Them Unwanted switching at the outputs Occur because delay paths through the circuit experience different propagation delays Danger if logic "makes a decision" while output is unstable OR hazard output controls an asynchronous input (these respond immediately to changes rather than waiting for a synchronizing signal called a clock) Solutions: wait until signals are stable (by using a clock) never use circuits with asynchronous inputs design hazard-free circuits (single-bit changes in the inputs) Time Response in Combinational Networks

7
Hazards/Glitches and How to Avoid Them Kinds of Hazards Input change causes output to go from 1 to 0 to 1 Input change causes output to go from 0 to 1 to 0 Input change causes a double change from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0 Time Response in Combinational Networks

8
Time Response in Combinational Circuits Glitch Example F = A' D + A C' input change within product term input change that spans product terms output changes from 1 to 0 to 1 G1 G2 G3 A \C \A D F G1 G2 G3 A \C \A D F 1 1 1 1 0 0 0 1 1 1 1 0 0 0 ABCD = 1100 ABCD = 1101 G1 G2 G3 A \C \A D F G1 G2 G3 A \C \A D F 0 1 0 0 1 0 0 1 1 1 1 1 0 0 ABCD = 1101 ABCD = 0101 (A is still 0) G1 G2 G3 A \C \A D F 0 1 0 1 1 1 1 ABCD = 0101 (A is 1)

9
Time Response in Combinational Networks Glitch Example General Strategy: add redundant terms F = A' D + A C' becomes A' D + A C' + C' D This eliminates 1-hazard? How about 0-hazard? Re-express F in PoS form: F = (A' + C')(A + D) Glitch present! Add term: (C' + D) This expression is equivalent to the hazard-free SoP form of F

10
Time Response in Combinational Networks Glitch Example Start with expression that is free of static 1-hazards F = A C' + A' D + C' D F' = (A C' + A' D + C' D)' = (A' + C) (A + D') (C + D') = A C + A C D' + C D' + A' C D' + A' D' = A C + C D' + A' D' covers all the adjacent 0's in the K-map free of static-1 and static-0 hazards! Work with complement:

11
Time Response in Combinational Networks Static hazards Solution: Add redundant terms to insure all adjacent transitions are covered by terms F2 = A C' + A' D + C' D + A B + B D 1's hazards in F corrected in F2

12
Time Response in Combinational Networks Designing Networks for Hazard-free operation Simply place transient output function in a form that guarantees that all adjacent ones are covered by a term no term of the transient output function contains both a variable and its complement F(A,B,C,D) = m(1,3,5,7,8,9,12,13,14,15) F = A B + A' D + B D + A C' + C' D = (A' + B + C') D + A (B + C') (factored by distributive law, which does not introduce hazards since it does not depend on the complementarity laws for its validity)

13
Time Response in Combinational Networks Dynamic Hazards Example with Dynamic Hazard Three different paths from B or B' to output ABC = 000, F = 1 to ABC = 010, F = 0 different delays along the paths: G1 slow, G4 very slow Handling dynamic hazards very complex Beyond our scope

Similar presentations

OK

EECC341 - Shaaban #1 Lec # 8 Winter 2001 1-9-2002 Combinational Logic Circuit Transient Vs. Steady-state Output Gate propagation delay: The time between.

EECC341 - Shaaban #1 Lec # 8 Winter 2001 1-9-2002 Combinational Logic Circuit Transient Vs. Steady-state Output Gate propagation delay: The time between.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on spiritual leadership book Ppt on polluted ganga river Ppt on raft foundation of buildings Ppt on principles of object-oriented programming Ppt on chapter natural resources Ppt on group decision making Ppt on types of houses Ppt on energy resources and conservation Ppt on sanskritization definition Ppt on bluetooth broadcasting hardware